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2020 – today
- 2023
[j12]Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta
, Koji Yamazaki, Kimikazu Sano:
High-definition technology of AI inference scheme for object detection on edge/terminal. IEICE Electron. Express 20(13): 20232002 (2023)- [j11]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023) - 2022
- [c13]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3 - [c12]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - 2021
- [j10]Saki Hatta, Nobuyuki Tanaka, Hiroyuki Uzawa, Koyo Nitta:
Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems. IEICE Trans. Commun. 104-B(3): 277-285 (2021) - [j9]Hiroyuki Uzawa, Kazuhiko Terada, Koyo Nitta:
A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation. IEICE Trans. Commun. 104-B(5): 481-489 (2021) - [j8]Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta:
FPGA-based network microburst analysis system with efficient packet capturing. JOCN 13(10): E72-E80 (2021) - 2020
- [j7]Yuta Ukon, Koji Yamazaki, Koyo Nitta:
Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture. IEICE Trans. Commun. 103-B(1): 11-19 (2020) - [j6]Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. 103-C(3): 77-84 (2020) - [c11]Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta:
FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing. ASAP 2020: 29-32
2010 – 2019
- 2019
- [c10]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3 - 2018
- [j5]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1930-1938 (2018) - [c9]Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki:
Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane. HPSR 2018: 1-6 - [c8]Yuta Ukon, Koji Yamazaki, Koyo Nitta:
Video Service Function Chaining with a Real-time Packet Reordering Circuit. ISCAS 2018: 1-5 - 2015
- [b1]Koyo Nitta:
Motion Estimation and Compensation Hardware Architecture with Hierarchy of Flexibility in Video Encoder LSIs. Kyoto University, Japan, 2015 - [c7]Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu:
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. Hot Chips Symposium 2015: 1-24 - [c6]Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu:
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability. VLSIC 2015: 54- - 2013
- [c5]Jia Su, Koyo Nitta, Mitsuo Ikeda, Atsushi Shimizu:
Residue role assignment based transform partition predetermination on HEVC. ICIP 2013: 2019-2023 - 2012
- [j4]Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma:
An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures. IEICE Trans. Electron. 95-C(4): 432-440 (2012) - [c4]Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa:
MVC real-time video encoder for full-HDTV 3D video. ICCE 2012: 166-167
2000 – 2009
- 2008
- [c3]Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma:
Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI. ISCAS 2008: 800-803 - 2007
- [j3]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima:
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1055-1059 (2007) - 2003
- [c2]Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo:
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level. DATE 2003: 20002-20007
1990 – 1999
- 1999
- [j2]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai:
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19(4): 56-65 (1999) - [j1]Takeshi Yoshitome, Toshihiro Minami, Mitsuo Ikeda, Koyo Nitta, Kazuhito Suguri:
A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI. IEEE Trans. Consumer Electron. 45(4): 1130-1133 (1999) - [c1]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE 1999: 44-
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