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ORCIDAyan Banerjee 0003
Person information
- affiliation: Indian Institute of Engineering Science and Technology Shibpur, Howrah, India
Other persons with the same name
- Ayan Banerjee — disambiguation page
- Ayan Banerjee 0001
![[0000-0001-6529-1644]](https://dblp.org/img/orcid-mark.12x12.png "0000-0001-6529-1644")
— Arizona State University, Tempe, AZ, USA - Ayan Banerjee 0002 — Jalpaiguri Govt. Engineering College, Jalpaiguri, India
- Ayan Banerjee 0004 — IIT Kanpur, Kanpur, India
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2020 – today
- 2024
[c9]Moitreya Chaudhury, Binit Kumar Pandit, Ayan Banerjee:
A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans. VDAT 2024: 1-6- 2023
- [j20]Binit Kumar Pandit, Ayan Banerjee:
3D EdgeSegNET: a deep neural network framework for simultaneous edge detection and segmentation of medical images. Signal Image Video Process. 17(6): 2981-2989 (2023) - [c8]Akash Ther, Binit Kumar Pandit, Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee:
Resource-efficient VLSI Architecture of Softmax Activation Function for Real-time Inference in Deep Learning Applications. ISDCS 2023: 1-5 - 2022
- [j19]Anirban Ganguly, Ayan Banerjee:
A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method. Circuits Syst. Signal Process. 41(9): 5201-5225 (2022) - [j18]Debanjana Datta, Ayan Banerjee:
Systematic realization of non-linear arithmetic functions using hexagonal Field Programmable Analog Array. Microelectron. J. 126: 105495 (2022) - [j17]Ayan Banerjee, Chinmoy Ghosh, Satyendra Nath Mandal:
Analysis of V-Net Architecture for Iris Segmentation in Unconstrained Scenarios. SN Comput. Sci. 3(3): 208 (2022) - [j16]Baidyanath Ray, Debanjana Datta, Mousumi Bhanja, Ayan Banerjee:
Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5152-5168 (2022) - 2021
- [j15]Ayan Banerjee, Anindya Sundar Dhar:
A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation. Circuits Syst. Signal Process. 40(1): 311-334 (2021) - [j14]Anirban Ganguly, Ayan Banerjee:
Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end. Microelectron. J. 115: 105184 (2021) - [j13]Ayan Banerjee, Anirban Kundu:
Cloud Based e-Feedback Services Using Performance Analysis: A Linear Approach. Trans. Large Scale Data Knowl. Centered Syst. 47: 181-212 (2021) - [j12]Anirban Chakraborty, Ayan Banerjee:
CORDIC-Based High-Speed VLSI Architecture of Transform Model Estimation for Real-Time Imaging. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 215-226 (2021) - [j11]Ayan Banerjee, Anirban Kundu:
Cellular Automata based Cryptography Model for Reliable Encryption Using State Transition in Wireless Network Optimizing Data Security. Wirel. Pers. Commun. 119(1): 877-918 (2021) - [c7]Binit Kumar Pandit, Ayan Banerjee:
VLSI Architecture of Sigmoid Activation Function for Rapid Prototyping of Machine Learning Applications. iSES 2021: 117-122 - 2020
- [j10]Anirban Chakraborty, Ayan Banerjee:
A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic. J. Circuits Syst. Comput. 29(9): 2050151:1-2050151:29 (2020) - [j9]Anirban Chakraborty, Ayan Banerjee:
A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition. J. Real Time Image Process. 17(5): 1421-1446 (2020) - [c6]Ayan Banerjee, Anirban Kundu:
Comparative Analysis of Cellular Automata Based Multilingual Encryption Using Syndicate Rules for Data Security. IBICA 2020: 301-310
2010 – 2019
- 2019
- [j8]Ayan Banerjee, Anirban Kundu:
Software for Feedback System Using Adaptive Categorization and Authenticated Recommendation. Int. J. Open Source Softw. Process. 10(2): 37-69 (2019) - [j7]Anirban Chakraborty, Ayan Banerjee:
Modular and parallel VLSI architecture of multi-dimensional quad-core GA co-processor for real time image/video processing. Microprocess. Microsystems 65: 180-195 (2019) - [j6]Debolina Chakraborty, Milan Kumar Tarafder, Ayan Banerjee, Sekhar R. Bhadra Chaudhuri:
Gabor-based spectral domain automated notch-reject filter for quasi-periodic noise reduction from digital images. Multim. Tools Appl. 78(2): 1757-1783 (2019) - [j5]Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee, S. R. Bhadra Chaudhuri:
A unified block-based sparse domain solution for quasi-periodic de-noising from different genres of images with iterative filtering. Multim. Tools Appl. 78(18): 26759-26785 (2019) - [c5]Debanjana Datta, Baidyanath Ray, Ayan Banerjee:
Synthesis of Linear and Non-linear Analog Circuits. SoCC 2019: 193-194 - [c4]Debanjana Datta, Mousumi Bhanja, Anirban Chaudhuri, Baidyanath Ray, Ayan Banerjee:
Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits. SoCC 2019: 455-460 - [c3]Debanjana Datta, Sweta Agarwal, Vikash Kumar, Mayank Raj, Baidyanath Ray, Ayan Banerjee:
Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function. VDAT 2019: 47-60 - 2018
- [j4]Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee, Sekhar R. Bhadra Chaudhuri:
Automated spectral domain approach of quasi-periodic denoising in natural images using notch filtration with exact noise profile. IET Image Process. 12(7): 1150-1163 (2018) - [c2]Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee:
A Highly Accurate Current Mode Analog Implementation of Radix-2 FFT/IFFT Processor. ISED 2018: 90-94 - [c1]Anirban Chakraborty, Ayan Banerjee:
Low Area & Memory Efficient VLSI Architecture of 1D/2D DWT for Real Time Image Decomposition. ISED 2018: 116-123 - 2013
- [j3]Ayan Banerjee, Anindya Sundar Dhar:
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer. J. Signal Process. Syst. 70(1): 39-48 (2013)
2000 – 2009
- 2005
- [j2]Ayan Banerjee, Anindya Sundar Dhar:
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation. Microprocess. Microsystems 29(7): 351-357 (2005) - 2001
- [j1]Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee:
FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocess. Microsystems 25(3): 131-142 (2001)
Coauthor Index
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last updated on 2024-12-02 21:29 CET by the dblp team
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