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dblp: Yoshihiko Horio https://dblp.org/pid/82/162.html dblp person page RSS feed Sat, 21 Sep 2024 01:47:27 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Yoshihiko Horiohttps://dblp.org/pid/82/162.html14451 Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing.https://doi.org/10.1109/IJCNN60899.2024.10649999, , , , , , :
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. IJCNN : 1-6]]>https://dblp.org/rec/conf/ijcnn/MoriyaYIYHMS24Mon, 01 Jan 2024 00:00:00 +0100 Analysis of Learning Process of Synaptic Weights in Spatio-temporal Learning Networks for Hardware Implementation.https://doi.org/10.1109/IJCNN60899.2024.10650861, , :
Analysis of Learning Process of Synaptic Weights in Spatio-temporal Learning Networks for Hardware Implementation. IJCNN : 1-8]]>https://dblp.org/rec/conf/ijcnn/OrimaHT24Mon, 01 Jan 2024 00:00:00 +0100 An event-driven mixed analog/digital spiking neural network circuit model for hippocampal spatiotemporal context learning and memory.https://doi.org/10.1109/IJCNN60899.2024.10650476, , :
An event-driven mixed analog/digital spiking neural network circuit model for hippocampal spatiotemporal context learning and memory. IJCNN : 1-8]]>https://dblp.org/rec/conf/ijcnn/TsujiOH24Mon, 01 Jan 2024 00:00:00 +0100 Bifurcation phenomena observed from two-variable spiking neuron integrated circuit.https://doi.org/10.1109/ISCAS58744.2024.10558075, , , :
Bifurcation phenomena observed from two-variable spiking neuron integrated circuit. ISCAS : 1-5]]>https://dblp.org/rec/conf/iscas/OrimaHMS24Mon, 01 Jan 2024 00:00:00 +0100 An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation.https://doi.org/10.1016/j.procs.2023.08.186, , :
An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation. INNS DLIA@IJCNN : 478-487]]>https://dblp.org/rec/conf/inns-dlia/OrimaTH23Sun, 01 Jan 2023 00:00:00 +0100 Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function.https://doi.org/10.1109/TCSI.2022.3140762, , , :
Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1655-1667 ()]]>https://dblp.org/rec/journals/tcasI/OnukiCHM22Sat, 01 Jan 2022 00:00:00 +0100 A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation.https://doi.org/10.1109/IJCNN55064.2022.9891920, , , , , :
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN : 1-7]]>https://dblp.org/rec/conf/ijcnn/MoriyaYSYHM22Sat, 01 Jan 2022 00:00:00 +0100 Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit.https://doi.org/10.1109/3DIC52383.2021.9687614, , , :
Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. 3DIC : 1-4]]>https://dblp.org/rec/conf/3dic/HorioOKK21Fri, 01 Jan 2021 00:00:00 +0100 Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing.https://doi.org/10.1109/3DIC52383.2021.9687608, , , , , :
Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC : 1-4]]>https://dblp.org/rec/conf/3dic/KiyoyamaHFHOK21Fri, 01 Jan 2021 00:00:00 +0100 A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model.https://doi.org/10.1007/978-3-030-86383-8_14, , , , , , :
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) : 177-181]]>https://dblp.org/rec/conf/icann/SatoMKYHYM21Fri, 01 Jan 2021 00:00:00 +0100 An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation.https://doi.org/10.1007/978-3-030-30487-4_55, , , , , :
An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation. ICANN (1) : 718-723]]>https://dblp.org/rec/conf/icann/TamuraMKSHS19Tue, 01 Jan 2019 00:00:00 +0100 Chaotic Neural Network Reservoir.https://doi.org/10.1109/IJCNN.2019.8852265:
Chaotic Neural Network Reservoir. IJCNN : 1-5]]>https://dblp.org/rec/conf/ijcnn/Horio19Tue, 01 Jan 2019 00:00:00 +0100 Short-term Prediction of Hyperchaotic Flow Using Echo State Network.https://doi.org/10.1109/IJCNN.2019.8852150, , , , :
Short-term Prediction of Hyperchaotic Flow Using Echo State Network. IJCNN : 1-5]]>https://dblp.org/rec/conf/ijcnn/SinozakiSKMH19Tue, 01 Jan 2019 00:00:00 +0100 An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea.https://doi.org/10.2991/jrnal.2017.4.1.11, :
An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea. J. Robotics Netw. Artif. Life 4(1): 49-52 ()]]>https://dblp.org/rec/journals/jrnal/OrimaH17Sun, 01 Jan 2017 00:00:00 +0100 Beta encoders: Symbolic Dynamics and Electronic Implementation.https://doi.org/10.1142/S0218127412300315, , , :
Beta encoders: Symbolic Dynamics and Electronic Implementation. Int. J. Bifurc. Chaos 22(9) ()]]>https://dblp.org/rec/journals/ijbc/KohdaHTA12Sun, 01 Jan 2012 00:00:00 +0100 A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach.https://doi.org/10.1109/ECCTD.2011.6043293, , , , :
A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD : 126-129]]>https://dblp.org/rec/conf/ecctd/MorieAIHA11Sat, 01 Jan 2011 00:00:00 +0100 Forced chaos generator with switched CMOS active inductance.https://doi.org/10.1109/ECCTD.2011.6043624, , :
Forced chaos generator with switched CMOS active inductance. ECCTD : 640-643]]>https://dblp.org/rec/conf/ecctd/TsubakiHA11Sat, 01 Jan 2011 00:00:00 +0100 Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems.https://doi.org/10.1007/978-3-642-17537-4_7, , :
Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems. ICONIP (1) : 49-57]]>https://dblp.org/rec/conf/iconip/KawamuraHH10Fri, 01 Jan 2010 00:00:00 +0100 Foreword.https://doi.org/10.1587/transfun.E92.A.2498:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2498 ()]]>https://dblp.org/rec/journals/ieicet/Horio09Thu, 01 Jan 2009 00:00:00 +0100 Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits.https://doi.org/10.1109/ISCAS.2009.5118339, , , :
Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits. ISCAS : 2621-2624]]>https://dblp.org/rec/conf/iscas/AndoNHA09Thu, 01 Jan 2009 00:00:00 +0100 A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators.https://doi.org/10.1109/ISCAS.2009.5118396, , , :
A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators. ISCAS : 2850-2853]]>https://dblp.org/rec/conf/iscas/JinnoHDA09Thu, 01 Jan 2009 00:00:00 +0100 An IC implementation of a hysteresis two-port VCCS chaotic oscillator.https://doi.org/10.1109/ECCTD.2007.4529749, , :
An IC implementation of a hysteresis two-port VCCS chaotic oscillator. ECCTD : 926-929]]>https://dblp.org/rec/conf/ecctd/HamadaHA07Mon, 01 Jan 2007 00:00:00 +0100 An asynchronous spiking chaotic neuron integrated circuit.https://doi.org/10.1016/j.neucom.2004.09.001, , :
An asynchronous spiking chaotic neuron integrated circuit. Neurocomputing 64: 447-472 ()]]>https://dblp.org/rec/journals/ijon/HorioTA05Sat, 01 Jan 2005 00:00:00 +0100 A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems.https://doi.org/10.1016/j.neunet.2005.06.022, , :
A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems. Neural Networks 18(5-6): 505-513 ()]]>https://dblp.org/rec/journals/nn/HorioIA05Sat, 01 Jan 2005 00:00:00 +0100 One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source.https://doi.org/10.1109/ECCTD.2005.1522897, , :
One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. ECCTD : 11-14]]>https://dblp.org/rec/conf/ecctd/YagasakiHA05Sat, 01 Jan 2005 00:00:00 +0100 Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics.https://doi.org/10.1007/978-3-540-30132-5_133, , :
Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics. KES : 988-994]]>https://dblp.org/rec/conf/kes/HorioOM04Thu, 01 Jan 2004 00:00:00 +0100 Neuron-synapse IC chip-set for large-scale chaotic neural networks.https://doi.org/10.1109/TNN.2003.816349, , :
Neuron-synapse IC chip-set for large-scale chaotic neural networks. IEEE Trans. Neural Networks 14(5): 1393-1404 ()]]>https://dblp.org/rec/journals/tnn/HorioAY03Wed, 01 Jan 2003 00:00:00 +0100 An integrated multi-scroll circuit with floating-gate MOSFETs.https://doi.org/10.1109/ISCAS.2003.1204985, , :
An integrated multi-scroll circuit with floating-gate MOSFETs. ISCAS (3) : 180-183]]>https://dblp.org/rec/conf/iscas/FujiwaraHA03Wed, 01 Jan 2003 00:00:00 +0100 Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent.https://doi.org/10.1109/ISCAS.2001.921327, :
Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent. ISCAS (3) : 381-384]]>https://dblp.org/rec/conf/iscas/NagataH01Mon, 01 Jan 2001 00:00:00 +0100 A simulated LC oscillator using multi-input floating-gate MOSFETS.https://doi.org/10.1109/ISCAS.2001.921444, , :
A simulated LC oscillator using multi-input floating-gate MOSFETS. ISCAS (3) : 763-766]]>https://dblp.org/rec/conf/iscas/HorioA01Mon, 01 Jan 2001 00:00:00 +0100 Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions.https://doi.org/10.1109/ISCAS.1999.777603, , , , :
Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions. ISCAS (5) : 438-441]]>https://dblp.org/rec/conf/iscas/HorioKKHA99Fri, 01 Jan 1999 00:00:00 +0100 An asynchronous pulse neural network model and its analog IC implementation.https://doi.org/10.1109/ICECS.1998.813995, , , :
An asynchronous pulse neural network model and its analog IC implementation. ICECS : 301-304]]>https://dblp.org/rec/conf/icecsys/HorioYHA98Thu, 01 Jan 1998 00:00:00 +0100 Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression.https://doi.org/10.1109/89.536931, , , , , :
Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression. IEEE Trans. Speech Audio Process. 4(5): 379-382 ()]]>https://dblp.org/rec/journals/taslp/SaitoUSNHK96Mon, 01 Jan 1996 00:00:00 +0100 Switched-current chaotic neural network with chaotic simulated annealing.https://doi.org/10.1109/ICNN.1995.487287, :
Switched-current chaotic neural network with chaotic simulated annealing. ICNN : 3146-3149]]>https://dblp.org/rec/conf/icnn/KanouH95Sun, 01 Jan 1995 00:00:00 +0100 Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons.https://doi.org/10.1109/ISCAS.1995.521542, :
Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. ISCAS : 429-432]]>https://dblp.org/rec/conf/iscas/HorioS95Sun, 01 Jan 1995 00:00:00 +0100 IC Implementation of Switched-Capacitor Chaotic Neuron.https://doi.org/10.1109/ISCAS.1994.409535, :
IC Implementation of Switched-Capacitor Chaotic Neuron. ISCAS : 97-100]]>https://dblp.org/rec/conf/iscas/HorioS94Sat, 01 Jan 1994 00:00:00 +0100 Switched-capacitor Chaotic Neuron for Chaotic Neural Networks.https://dblp.org/pid/82/162.html, :
Switched-capacitor Chaotic Neuron for Chaotic Neural Networks. ISCAS : 1018-1021]]>https://dblp.org/rec/conf/iscas/HorioS93Fri, 01 Jan 1993 00:00:00 +0100 A simple method for designing a hierarchical structure transversal filter.https://doi.org/10.1109/ICASSP.1991.150791, , , :
A simple method for designing a hierarchical structure transversal filter. ICASSP : 1993-1996]]>https://dblp.org/rec/conf/icassp/KawahashiNHK91Tue, 01 Jan 1991 00:00:00 +0100