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ORCIDYoshihiko Horio
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2020 – today
- 2024
[c30]Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato:
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. IJCNN 2024: 1-6- [c29]Takemori Orima, Yoshihiko Horio, Takeru Tsuji:
Analysis of Learning Process of Synaptic Weights in Spatio-temporal Learning Networks for Hardware Implementation. IJCNN 2024: 1-8 - [c28]Takeru Tsuji, Takemori Orima, Yoshihiko Horio:
An event-driven mixed analog/digital spiking neural network circuit model for hippocampal spatiotemporal context learning and memory. IJCNN 2024: 1-8 - [c27]Takemori Orima, Yoshihiko Horio, Satoshi Moriya, Shigeo Sato:
Bifurcation phenomena observed from two-variable spiking neuron integrated circuit. ISCAS 2024: 1-5 - 2023
- [c26]Takemori Orima
, Takeru Tsuji, Yoshihiko Horio:
An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation. INNS DLIA@IJCNN 2023: 478-487 - 2022
- [j8]Koshiro Onuki, Kenichiro Cho, Yoshihiko Horio, Takaya Miyano:
Secret-Key Exchange Through Synchronization of Randomized Chaotic Oscillators Aided by Logistic Hash Function. IEEE Trans. Circuits Syst. I Regul. Pap. 69(4): 1655-1667 (2022) - [c25]Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas:
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN 2022: 1-7 - 2021
- [c24]Yoshihiko Horio, Takemori Orima, Koji Kiyoyama, Mitsumasa Koyanagi:
Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. 3DIC 2021: 1-4 - [c23]Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi:
Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC 2021: 1-4 - [c22]Shigeo Sato, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto, Yoshihiko Horio, Yasushi Yuminaka, Jordi Madrenas:
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) 2021: 177-181
2010 – 2019
- 2019
- [c21]Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Yoshihiko Horio, Shigeo Sato:
An Izhikevich Model Neuron MOS Circuit for Low Voltage Operation. ICANN (1) 2019: 718-723 - [c20]Yoshihiko Horio:
Chaotic Neural Network Reservoir. IJCNN 2019: 1-5 - [c19]Aren Sinozaki, Kota Shiozawa, Kazuki Kajita, Takaya Miyano, Yoshihiko Horio:
Short-term Prediction of Hyperchaotic Flow Using Echo State Network. IJCNN 2019: 1-5 - 2017
- [j7]Takemori Orima, Yoshihiko Horio:
An Improved Parameter Value Optimization Technique for the Reflectionless Transmission-Line Model of the Cochlea. J. Robotics Netw. Artif. Life 4(1): 49-52 (2017) - 2012
- [j6]Tohru Kohda, Yoshihiko Horio, Yoichiro Takahashi, Kazuyuki Aihara:
Beta encoders: Symbolic Dynamics and Electronic Implementation. Int. J. Bifurc. Chaos 22(9) (2012) - 2011
- [c18]Takashi Morie, Daisuke Atuti, Kazuki Ifuku, Yoshihiko Horio, Kazuyuki Aihara:
A CMOS nonlinear-map circuit array for threshold-coupled chaotic maps using pulse-modulation approach. ECCTD 2011: 126-129 - [c17]Yusuke Tsubaki, Yoshihiko Horio, Kazuyuki Aihara:
Forced chaos generator with switched CMOS active inductance. ECCTD 2011: 640-643 - 2010
- [c16]Tetsuo Kawamura, Yoshihiko Horio, Mikio Hasegawa:
Mutual Information Analyses of Chaotic Neurodynamics Driven by Neuron Selection Methods in Synchronous Exponential Chaotic Tabu Search for Quadratic Assignment Problems. ICONIP (1) 2010: 49-57
2000 – 2009
- 2009
- [j5]Yoshihiko Horio:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(10): 2498 (2009) - [c15]Hiroyasu Ando, Aki Nakano, Yoshihiko Horio, Kazuyuki Aihara:
Adaptive Feedback Control of Chaotic Neurodynamics in Analog Circuits. ISCAS 2009: 2621-2624 - [c14]Kenya Jin'no, Yoshihiko Horio, Ryosuke Domae, Kazuyuki Aihara:
A Multi-hysteresis VCCS and its Application to Multi-scroll Chaotic Oscillators. ISCAS 2009: 2850-2853 - 2007
- [c13]Takuya Hamada, Yoshihiko Horio, Kazuyuki Aihara:
An IC implementation of a hysteresis two-port VCCS chaotic oscillator. ECCTD 2007: 926-929 - 2005
- [j4]Yoshihiko Horio, Takuya Taniguchi, Kazuyuki Aihara:
An asynchronous spiking chaotic neuron integrated circuit. Neurocomputing 64: 447-472 (2005) - [j3]Yoshihiko Horio, Tohru Ikeguchi, Kazuyuki Aihara:
A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems. Neural Networks 18(5-6): 505-513 (2005) - [c12]Tomoumi Yagasaki, Yoshihiko Horio, Kazuyuki Aihara:
One-dimensional discrete-time dynamical systems circuit using floating-gate MOS peaking current sink/source. ECCTD 2005: 11-14 - 2004
- [c11]Yoshihiko Horio, Takahide Okuno, Koji Mori:
Switched-Capacitor Large-Scale Chaotic Neuro-Computer Prototype and Chaotic Search Dynamics. KES 2004: 988-994 - 2003
- [j2]Yoshihiko Horio, Kazuyuki Aihara, O. Yamamoto:
Neuron-synapse IC chip-set for large-scale chaotic neural networks. IEEE Trans. Neural Networks 14(5): 1393-1404 (2003) - [c10]Tetsuya Fujiwara, Yoshihiko Horio, Kazuyuki Aihara:
An integrated multi-scroll circuit with floating-gate MOSFETs. ISCAS (3) 2003: 180-183 - 2001
- [c9]Shinya Nagata, Yoshihiko Horio:
Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent. ISCAS (3) 2001: 381-384 - [c8]Kinya Matsuda, Yoshihiko Horio, Kazuyuki Aihara:
A simulated LC oscillator using multi-input floating-gate MOSFETS. ISCAS (3) 2001: 763-766
1990 – 1999
- 1999
- [c7]Yoshihiko Horio, Izumi Kobayashi, Masato Kawakami, Hiroshi Hayashi, Kazuyuki Aihara:
Switched-capacitor multi-internal-state chaotic neuron circuit with unipolar and bipolar output functions. ISCAS (5) 1999: 438-441 - 1998
- [c6]Yoshihiko Horio, Hidekazu Yasuda, Mitsuru Hanagata, Kazuyuki Aihara:
An asynchronous pulse neural network model and its analog IC implementation. ICECS 1998: 301-304 - 1996
- [j1]Hiroto Saito, Isao Umoto, Akira Sasou, Shogo Nakamura, Yoshihiko Horio, Tahiro Kubota:
Subadaptive piecewise linear quantization for speech signal (64 kbit/s) compression. IEEE Trans. Speech Audio Process. 4(5): 379-382 (1996) - 1995
- [c5]Nobuo Kanou, Yoshihiko Horio:
Switched-current chaotic neural network with chaotic simulated annealing. ICNN 1995: 3146-3149 - [c4]Yoshihiko Horio, Ken Suyama:
Dynamic Associative Memory Using Switched-Capacitor Chaotic Neurons. ISCAS 1995: 429-432 - 1994
- [c3]Yoshihiko Horio, Ken Suyama:
IC Implementation of Switched-Capacitor Chaotic Neuron. ISCAS 1994: 97-100 - 1993
- [c2]Yoshihiko Horio, Ken Suyama:
Switched-capacitor Chaotic Neuron for Chaotic Neural Networks. ISCAS 1993: 1018-1021 - 1991
- [c1]Akiyoshi Kawahashi, Shogo Nakanura, Yoshihiko Horio, Yukio Kadowaki:
A simple method for designing a hierarchical structure transversal filter. ICASSP 1991: 1993-1996
Coauthor Index
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