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dblp: Ilya Ganusov https://dblp.org/pid/80/4703.html dblp person page RSS feed Thu, 25 Apr 2024 05:43:01 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Ilya Ganusovhttps://dblp.org/pid/80/4703.html14451 Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming.https://doi.org/10.1109/FPL53798.2021.00064Grace Zgheib, Yu Shen Lu, Ilya Ganusov:
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. FPL 2021: 327-333]]>https://dblp.org/rec/conf/fpl/ZgheibLG21Fri, 01 Jan 2021 00:00:00 +0100 Architectural Enhancements in Intel® Agilex™ FPGAs.https://doi.org/10.1145/3373087.3375308Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How

, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov:
Architectural Enhancements in Intel® Agilex™ FPGAs. FPGA 2020: 140-149]]>https://dblp.org/rec/conf/fpga/ChromczakWCHLVZ20Wed, 01 Jan 2020 00:00:00 +0100 Agilex™ Generation of Intel® FPGAs.https://doi.org/10.1109/HCS49909.2020.9220557Ilya K. Ganusov, Mahesh A. Iyer

, Ning Cheng, Alon Meisler:
Agilex™ Generation of Intel® FPGAs. Hot Chips Symposium 2020: 1-26]]>https://dblp.org/rec/conf/hotchips/GanusovICM20Wed, 01 Jan 2020 00:00:00 +0100 A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform.https://doi.org/10.1109/MM.2016.18Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro 36(2): 48-62 (2016)]]>https://dblp.org/rec/journals/micro/AhmadBGKRW16Fri, 01 Jan 2016 00:00:00 +0100 Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs.https://doi.org/10.1109/FPL.2016.7577343Ilya Ganusov, Benjamin Devlin:
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs. FPL 2016: 1-9]]>https://dblp.org/rec/conf/fpl/GanusovD16Fri, 01 Jan 2016 00:00:00 +0100 Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs.https://doi.org/10.1109/FPL.2016.7577344Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das:
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. FPL 2016: 1-10]]>https://dblp.org/rec/conf/fpl/GanusovFNPD16Fri, 01 Jan 2016 00:00:00 +0100 UltraScale+ MPSoC and FPGA families.https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2015.7477457Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
UltraScale+ MPSoC and FPGA families. Hot Chips Symposium 2015: 1-37]]>https://dblp.org/rec/conf/hotchips/BoppanaAGKRW15Thu, 01 Jan 2015 00:00:00 +0100 Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.https://doi.org/10.1145/1187976.1187979Ilya Ganusov, Martin Burtscher:
Future execution: A prefetching mechanism that uses multiple cores to speed up single threads. ACM Trans. Archit. Code Optim. 3(4): 424-449 (2006)]]>https://dblp.org/rec/journals/taco/GanusovB06Sun, 01 Jan 2006 00:00:00 +0100 Efficient emulation of hardware prefetchers via event-driven helper threading.https://doi.org/10.1145/1152154.1152178Ilya Ganusov, Martin Burtscher:
Efficient emulation of hardware prefetchers via event-driven helper threading. PACT 2006: 144-153]]>https://dblp.org/rec/conf/IEEEpact/GanusovB06Sun, 01 Jan 2006 00:00:00 +0100 Bridging the Processor-Memory Performance Gapwith 3D IC Technology.https://doi.org/10.1109/MDT.2005.134Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari:
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. IEEE Des. Test Comput. 22(6): 556-564 (2005)]]>https://dblp.org/rec/journals/dt/LiuGBT05Sat, 01 Jan 2005 00:00:00 +0100 The VPC Trace-Compression Algorithms.https://doi.org/10.1109/TC.2005.186Martin Burtscher, Ilya Ganusov, Sandra J. Jackson, Jian Ke, Paruj Ratanaworabhan, Nana B. Sam:
The VPC Trace-Compression Algorithms. IEEE Trans. Computers 54(11): 1329-1344 (2005)]]>https://dblp.org/rec/journals/tc/BurtscherGJKRS05Sat, 01 Jan 2005 00:00:00 +0100 On the importance of optimizing the configuration of stream prefetchers.https://doi.org/10.1145/1111583.1111591Ilya Ganusov, Martin Burtscher:
On the importance of optimizing the configuration of stream prefetchers. Memory System Performance 2005: 54-61]]>https://dblp.org/rec/conf/ACMmsp/GanusovB05Sat, 01 Jan 2005 00:00:00 +0100 Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors.https://doi.org/10.1109/PACT.2005.23Ilya Ganusov, Martin Burtscher:
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors. IEEE PACT 2005: 350-360]]>https://dblp.org/rec/conf/IEEEpact/GanusovB05Sat, 01 Jan 2005 00:00:00 +0100 Automatic Synthesis of High-Speed Processor Simulators.https://doi.org/10.1109/MICRO.2004.7Martin Burtscher, Ilya Ganusov:
Automatic Synthesis of High-Speed Processor Simulators. MICRO 2004: 55-66]]>https://dblp.org/rec/conf/micro/BurtscherG04Thu, 01 Jan 2004 00:00:00 +0100