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2020 – today
- 2021
[c10]Grace Zgheib, Yu Shen Lu, Ilya Ganusov:
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming. FPL 2021: 327-333- 2020
- [c9]Jeffrey Chromczak, Mark Wheeler, Charles Chiasson, Dana How
, Martin Langhammer, Tim Vanderhoek, Grace Zgheib, Ilya Ganusov:
Architectural Enhancements in Intel® Agilex™ FPGAs. FPGA 2020: 140-149 - [c8]Ilya K. Ganusov, Mahesh A. Iyer, Ning Cheng, Alon Meisler:
Agilex™ Generation of Intel® FPGAs. Hot Chips Symposium 2020: 1-26
2010 – 2019
- 2016
- [j4]Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro 36(2): 48-62 (2016) - [c7]Ilya Ganusov, Benjamin Devlin:
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs. FPL 2016: 1-9 - [c6]Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das:
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. FPL 2016: 1-10 - 2015
- [c5]Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
UltraScale+ MPSoC and FPGA families. Hot Chips Symposium 2015: 1-37
2000 – 2009
- 2006
- [j3]Ilya Ganusov, Martin Burtscher:
Future execution: A prefetching mechanism that uses multiple cores to speed up single threads. ACM Trans. Archit. Code Optim. 3(4): 424-449 (2006) - [c4]Ilya Ganusov, Martin Burtscher:
Efficient emulation of hardware prefetchers via event-driven helper threading. PACT 2006: 144-153 - 2005
- [j2]Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari:
Bridging the Processor-Memory Performance Gapwith 3D IC Technology. IEEE Des. Test Comput. 22(6): 556-564 (2005) - [j1]Martin Burtscher, Ilya Ganusov, Sandra J. Jackson, Jian Ke, Paruj Ratanaworabhan, Nana B. Sam:
The VPC Trace-Compression Algorithms. IEEE Trans. Computers 54(11): 1329-1344 (2005) - [c3]Ilya Ganusov, Martin Burtscher:
On the importance of optimizing the configuration of stream prefetchers. Memory System Performance 2005: 54-61 - [c2]Ilya Ganusov, Martin Burtscher:
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors. IEEE PACT 2005: 350-360 - 2004
- [c1]Martin Burtscher, Ilya Ganusov:
Automatic Synthesis of High-Speed Processor Simulators. MICRO 2004: 55-66
Coauthor Index
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