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2010 – 2019
- 2019
[c13]Kenta Morita, Haruhiko Takase, Naoki Morita, Hiroharu Kawanaka, Hidehiko Kita:
Spiking Neural Network to Extract Frequent Words from Japanese Speech Data. KES 2019: 363-371- 2018
- [c12]Kenta Morita, Haruhiko Takase, Masachika Sawamura, Naoki Morita, Hidehiko Kita:
Extraction of Frequent Sequential Patterns from Sequence at Uneven Intervals. SCIS&ISIS 2018: 1437-1441
2000 – 2009
- 2009
- [c11]Haruhiko Takase, Masaru Fujita, Hiroharu Kawanaka, Shinji Tsuruoka, Hidehiko Kita, Terumine Hayashi:
Obstacle to training SpikeProp networks - Cause of surges in training process -. IJCNN 2009: 3062-3066 - 2008
- [c10]Masaru Fujita, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi:
Shape of error surfaces in SpikeProp. IJCNN 2008: 840-844 - 2007
- [c9]Kazutaka Noro, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi, Naoki Morita:
Descriptive Answer Clustering System for Immediate Feedback. ICCE 2007: 37-40 - [c8]Haruhiko Takase, Masahiko Masahiko, Hidehiko Kita, Terumine Hayashi:
Enhancing both generalization and fault tolerance of multilayer neural networks. IJCNN 2007: 1429-1433 - 2006
- [c7]Terumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita:
Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing. ATS 2006: 327-332 - [c6]Haruhiko Takase, Hidehiko Kita, Terumine Hayashi:
Fault tolerant training algorithm for multi-layer neural networks focused on hidden unit activities. IJCNN 2006: 1540-1545 - 2005
- [j2]Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase:
On Test Data Compression Using Selective Don't-Care Identification. J. Comput. Sci. Technol. 20(2): 210-215 (2005) - 2004
- [c5]Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase:
Test data compression technique using selective don't-care identification. ASP-DAC 2004: 230-233 - 2003
- [c4]Yusei Katsuda, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi:
Manipulation of hidden units activities for fault tolerant multi-layer neural networks. CIRA 2003: 19-24 - 2001
- [j1]Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi:
An enhanced fault model for high defect coverage. Syst. Comput. Jpn. 32(6): 36-44 (2001) - 2000
- [c3]Haruhiko Takase, Tsuyoshi Shinogi, Terumine Hayashi, Hidehiko Kita:
Evaluation Function for Fault Tolerant Multi-Layer Neural Networks. IJCNN (3) 2000: 521-526
1990 – 1999
- 1997
- [c2]Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita:
An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. ASP-DAC 1997: 107-112
1980 – 1989
- 1984
- [c1]Hidehiko Kita, Toshiki Sakabe, Yasuyoshi Inagaki:
Algebraic Specification Method of Programming Languages. RIMS Symposia on Software Science and Engineering 1984: 144-157
Coauthor Index
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