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2020 – today
- 2024
[c35]Jai-Ming Lin
, You-Yu Chang, Wei-Lun Huang:
Timing-Driven Analytical Placement According to Expected Cell Distribution Range. ISPD 2024: 177-184- 2023
- [j22]Jai-Ming Lin, Tsung-Lin Tsai, Tsung-Chun Tsai:
Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package. IEEE Trans. Very Large Scale Integr. Syst. 31(9): 1308-1319 (2023) - [c34]Jai-Ming Lin, Yu-Chien Lin, Hsuan Kung, Wei-Yuan Lin:
HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique. ICCAD 2023: 1-8 - [c33]Jai-Ming Lin, Tsung-Chun Tsai, Rui-Ting Shen:
Routability-Driven Orientation-Aware Analytical Placement for System in Package. ICCAD 2023: 1-8 - [c32]Jai-Ming Lin, Yu-Tien Chen, Yang-Tai Kung, Hao-Jia Lin:
Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network. ISPD 2023: 35-43 - 2022
- [j21]Jai-Ming Lin, Liang-Chi Zane, Min-Chia Tsai, Yung-Chen Chen, Che-Li Lin, Chen-Fa Tsai:
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1783-1793 (2022) - [c31]Jai-Ming Lin, Po-Chen Lu, Heng-Yu Lin, Jia-Ting Tsai:
A Novel Blockage-Avoiding Macro Placement Approach for 3D ICs Based on POCS. ICCAD 2022: 118:1-118:7 - [c30]Jai-Ming Lin, Hao-Yuan Hsieh, Hsuan Kung, Hao-Jia Lin:
Routability-Driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs. ICCAD 2022: 119:1-119:8 - 2021
- [j20]Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Po-Chen Lu:
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 973-984 (2021) - [j19]Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 985-997 (2021) - [j18]Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1652-1664 (2021) - [c29]Jai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-Ting Wang, Po-Wen Wang:
DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit Designs. ICCAD 2021: 1-8 - [c28]Jai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai:
Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs. ICCAD 2021: 1-8 - [c27]Jai-Ming Lin, Yang-Tai Kung, Zheng-Yu Huang, I-Ru Chen:
A Fast Power Network Optimization Algorithm for Improving Dynamic IR-drop. ISPD 2021: 91-98
2010 – 2019
- 2019
- [j17]Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng:
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 57-68 (2019) - [c26]Jai-Ming Lin, Szu-Ting Li, Yi-Ting Wang:
Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros. DAC 2019: 119 - [c25]Jai-Ming Lin, You-Lun Deng, Ya-Chu Yang, Jia-Jian Chen, Yao-Chieh Chen:
A Novel Macro Placement Approach based on Simulated Evolution Algorithm. ICCAD 2019: 1-7 - 2018
- [c24]Jai-Ming Lin, Chien-Yu Huang:
General floorplanning methodology for 3D ICs with an arbitrary bonding style. DATE 2018: 1199-1202 - [c23]Jai-Ming Lin, Chien-Yu Huang, Jhih-Ying Yang:
Co-synthesis of floorplanning and powerplanning in 3D ICs for multiple supply voltage designs. DATE 2018: 1339-1344 - [c22]Jai-Ming Lin, Tai-Ting Chen, Yen-Fu Chang, Wei-Yi Chang, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu:
A fast thermal-aware fixed-outline floorplanning methodology based on analytical models. ICCAD 2018: 1:1-1:8 - [c21]Jai-Ming Lin, Jhih-Sheng Syu, I-Ru Chen:
Macro-aware row-style power delivery network design for better routability. ICCAD 2018: 15 - 2017
- [j16]Jai-Ming Lin, Jung-An Yang:
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1856-1868 (2017) - [c20]Jai-Ming Lin, Bo-Heng Yu, Li-Yen Chang:
Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits. ASP-DAC 2017: 438-443 - 2016
- [j15]Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang:
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10): 1730-1743 (2016) - [j14]Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang:
A Systematic Design Methodology of Asynchronous SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1835-1848 (2016) - [c19]Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin:
A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling. ASP-DAC 2016: 17-18 - [c18]Jai-Ming Lin, Po-Yang Chiu, Yen-Fu Chang:
SAINT: handling module folding and alignment in fixed-outline floorplans for 3D ICs. ICCAD 2016: 131 - 2015
- [j13]Jai-Ming Lin, Che-Chun Lin:
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 766-777 (2015) - [c17]Jai-Ming Lin, Chih-Yao Hu, Kai-Chung Chan:
Routability-driven floorplanning algorithm for mixed-size modules with fixed-outline constraint. VLSI-DAT 2015: 1-4 - 2014
- [j12]Jai-Ming Lin, Ji-Heng Wu:
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1681-1692 (2014) - [c16]Jai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang:
Current density aware power switch placement algorithm for power gating designs. ISPD 2014: 85-92 - 2013
- [j11]Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, Soon-Jyh Chang:
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 624-635 (2013) - 2012
- [j10]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1789-1802 (2012) - [j9]Jai-Ming Lin, Zhi-Xiong Hung:
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 473-484 (2012) - [c15]Jai-Ming Lin, Wei-Yi Cheng, Chung-Lin Lee, Richard C. Hsu:
Voltage island-driven floorplanning considering level shifter placement. ASP-DAC 2012: 443-448 - [c14]Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, Soon-Jyh Chang:
Analytical-based approach for capacitor placement with gradient error compensation and device correlation enhancement in analog integrated circuits. ICCAD 2012: 635-642 - [c13]Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin, Soon-Jyh Chang:
Routability-driven placement algorithm for analog integrated circuits. ISPD 2012: 71-78 - 2011
- [j8]Jai-Ming Lin, Zhi-Xiong Hung:
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(7): 1034-1044 (2011) - [c12]Jia-Ru Chuang, Jai-Ming Lin:
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction. ASP-DAC 2011: 527-532 - [c11]Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang:
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits. DAC 2011: 528-533 - 2010
- [c10]Jai-Ming Lin, Hsi Hung:
UFO: unified convex optimization algorithms for fixed-outline floorplanning. ASP-DAC 2010: 555-560 - [c9]Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang:
Performance-driven analog placement considering boundary constraint. DAC 2010: 292-297
2000 – 2009
- 2005
- [j7]Jai-Ming Lin, Yao-Wen Chang:
TCG: A transitive closure graph-based representation for general floorplans. IEEE Trans. Very Large Scale Integr. Syst. 13(2): 288-292 (2005) - [c8]Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang:
Placement with symmetry constraints for analog layout design using TCG-S. ASP-DAC 2005: 1135-1137 - 2004
- [j6]Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 968-980 (2004) - 2003
- [j5]Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin:
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 679-686 (2003) - [c7]Jai-Ming Lin, Song-Ra Pan, Yao-Wen Chang:
Graph matching-based algorithms for array-based FPGA segmentation design and routing. ASP-DAC 2003: 851-854 - 2002
- [j4]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
Performance-driven placement for dynamically reconfigurable FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 628-642 (2002) - [j3]Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 886-901 (2002) - [c6]Jai-Ming Lin, Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans. DAC 2002: 842-847 - [c5]Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG. DATE 2002: 69-75 - 2001
- [j2]Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong:
Matching-based algorithm for FPGA channel segmentation design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 784-791 (2001) - [j1]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
Generic ILP-based approaches for time-multiplexed FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1266-1274 (2001) - [c4]Jai-Ming Lin, Yao-Wen Chang:
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans. DAC 2001: 764-769 - [c3]Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang:
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning. ICCD 2001: 335-347 - [c2]Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang:
An Algorithm for Dynamically Reconfigurable FPGA Placement. ICCD 2001: 501-504
1990 – 1999
- 1998
- [c1]Yao-Wen Chang, Jai-Ming Lin, D. F. Wong:
Graph matching-based algorithms for FPGA segmentation design. ICCAD 1998: 34-39
Coauthor Index
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