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2020 – today
- 2024
[c12]Valeriy Sukharev, Jun-Ho Choy, Armen Kteyan, J. Shuster-Passage, Seungman Choi, Martin Gall:
A Unified Physics-Based Stochastic Model for EM-Induced Resistance Degradation in BEoL Interconnect Segments. IRPS 2024: 1-10- [c11]Yong Hyeon Yi, Chris H. Kim, Armen Kteyan, Alexander Volkov, Stéphane Moreau, Valeriy Sukharev:
Electromigration Test Chip Experiments from Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis. IRPS 2024: 1-6 - [c10]J. Shuster-Passage, S. Abdel Razek, M. Mattoo, Meike Hauschildt, Seungman Choi, Martin Gall, Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Matthias Kraatz, J. R. Lloyd:
A Novel Method for the Determination of Electromigration-Induced Void Nucleation Stresses. IRPS 2024: 10 - [c9]Jun-Ho Choy
, Stéphane Moreau, Catherine Brunet-Manquat, Valeriy Sukharev, Armen Kteyan:
Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects. ISPD 2024: 85-90 - 2023
- [c8]Yong Hyeon Yi, Chris H. Kim, Chen Zhou, Armen Kteyan, Valeriy Sukharev:
Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters. IRPS 2023: 1-5 - [c7]Armen Kteyan, Valeriy Sukharev, Alexander Volkov, Jun-Ho Choy, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Stéphane Moreau:
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution. ISPD 2023: 124-132 - 2022
- [j3]Valeriy Sukharev, Armen Kteyan, Farid N. Najm, Yong Hyeon Yi, Chris H. Kim, Jun-Ho Choy, Sofya Torosyan, Yu Zhu:
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4837-4850 (2022) - [c6]Armen Kteyan, Valeriy Sukharev, Y. Yi, Chris H. Kim:
Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited). IRPS 2022: 8 - [c5]Armen Kteyan, Jun-Ho Choy, Valeriy Sukharev, Massimo Bertoletti, Carmelo Maiorca, Rossana Zadra, Massimo Inzaghi, Gabriele Gattere, Giancarlo Zinco, Paolo Valente, Roberto Bardelli, Alessandro Valerio, Pierluigi Rolandi, Mattia Monetti, Valentina Cuomo, Salvatore Santapa:
Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance. ISPD 2022: 83-89
2010 – 2019
- 2019
- [c4]Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy:
An Accurate Assessment of Chip-Package Interaction is a Key Factor for Designing Resilient 3D IC Systems. 3DIC 2019: 1-6 - [c3]Armen Kteyan, Henrik Hovsepyan, Jun-Ho Choy, Valeriy Sukharev:
Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages. IRPS 2019: 1-7 - 2016
- [j2]Xin Huang, Armen Kteyan, Sheldon X.-D. Tan, Valeriy Sukharev:
Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11): 1848-1861 (2016) - 2015
- [c2]Jun-Ho Choy, Valeriy Sukharev, Armen Kteyan, Henrik Hovsepyan, Ramnath Venkatraman, Ruggero Castagnetti:
Post placement leakage reduction with stress-enhanced filler cells. ISLPED 2015: 303-308 - 2012
- [j1]Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan, Ara Markosian, Ehrenfried Zschech, Rene Huebner:
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance. J. Electron. Test. 28(1): 63-72 (2012)
2000 – 2009
- 2009
- [c1]Valeriy Sukharev, Ara Markosian, Armen Kteyan, Levon Manukyan, Nikolay Khachatryan, Jun-Ho Choy, Hasmik Lazaryan, Henrik Hovsepyan, Seiji Onoue, Takuo Kikuchi, Tetsuya Kamigaki:
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation. ISQED 2009: 156-161
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