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2010 – 2019
- 2017
[c7]Mika Laiho
, Mika Grönroos, Jussi H. Poikonen, Eero Lehtonen, Reon Katsumura, Atsushi T.-Fukuchi, Masashi Arita, Yasuo Takahashi:
Associative search using pseudo-analog memristors. ISCAS 2017: 1-4- 2016
- [j6]Jia Lee, Ferdinand Peper, Sorin Dan Cotofana, Makoto Naruse, Motoichi Ohtsu, Tadashi Kawazoe, Yasuo Takahashi, Tetsuya Shimokawa, Laszlo B. Kish, Tohru Kubota:
Brownian Circuits: Designs. Int. J. Unconv. Comput. 12(5-6): 341-362 (2016) - 2012
- [j5]Mingu Jo, Yuki Kato, Masashi Arita, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa, Yasuo Takahashi, Jung-Bum Choi:
Effect of Arrangement of Input Gates on Logic Switching Characteristics of Nanodot Array Device. IEICE Trans. Electron. 95-C(5): 865-870 (2012) - 2011
- [j4]Masakatsu Maeda, Takaaki Sato, Naoto Inoue, Daisuke Yagi, Yasuo Takahashi:
Anomalous microstructure formed at the interface between copper ribbon and tin-deposited copper plate by ultrasonic bonding. Microelectron. Reliab. 51(1): 130-136 (2011)
2000 – 2009
- 2009
- [j3]Takuya Kaizawa, Mingyu Jo, Masashi Arita, Akira Fujiwara, Kenji Yamazaki, Yukinori Ono, Hiroshi Inokawa, Yasuo Takahashi:
Full Adder Operation Based on Si Nanodot Array Device with Multiple Inputs and Outputs. Int. J. Nanotechnol. Mol. Comput. 1(2): 58-69 (2009) - 2007
- [j2]Wancheng Zhang, Katsuhiko Nishiguchi, Yukinori Ono, Akira Fujiwara, Hiroshi Yamaguchi, Hiroshi Inokawa, Yasuo Takahashi, Nan-Jian Wu:
Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors. IEICE Trans. Electron. 90-C(5): 943-948 (2007) - [j1]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13(3): 249-266 (2007) - 2006
- [c6]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2006: 19 - 2005
- [c5]Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2005: 32-38 - 2004
- [c4]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL 2004: 262-268 - [c3]Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274 - 2003
- [c2]Hiroshi Inokawa, Yasuo Takahashi:
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic. ISMVL 2003: 259-266 - 2000
- [c1]Yasuo Takahashi, Akira Fujiwara, Yukinori Ono, Katsumi Murase:
Silicon Single-Electron Devices and Their Applications. ISMVL 2000: 411-422
Coauthor Index
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