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2020 – today
- 2020
[c9]Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka:
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. VLSI Circuits 2020: 1-2- [c8]Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka:
A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. VLSI Circuits 2020: 1-2
2010 – 2019
- 2018
- [c7]Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka:
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. VLSI Circuits 2018: 19-20 - 2016
- [c6]Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii:
A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC 2016: 17-20 - 2015
- [c5]Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii:
1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. VLSIC 2015: 274- - 2014
- [c4]Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii:
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ISSCC 2014: 234-235 - 2013
- [j4]Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki:
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. IEEE J. Solid State Circuits 48(4): 917-923 (2013) - 2012
- [c3]Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki:
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. VLSIC 2012: 58-59
2000 – 2009
- 2009
- [c2]Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada:
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC 2009: 701-704 - 2007
- [j3]Masao Morimoto, Makoto Nagata
, Kazuo Taki:
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Trans. Electron. 90-C(4): 675-682 (2007) - 2005
- [j2]Masao Morimoto, Makoto Nagata, Kazuo Taki:
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Trans. Electron. 88-C(10): 2001-2008 (2005) - [j1]Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki:
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3324-3331 (2005) - 2002
- [c1]Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC 2002: 167-170
Coauthor Index
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