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ORCIDShih Ping Lin 0001
Person information
- affiliation: National Chiao Tung University, Department of Electronics Engineering, Hsinchu, Taiwan
Other persons with the same name
- Shih Ping Lin 0002 — National Taiwan University, Taipei, Taiwan
- Shih-Ping Lin 0002 — Asuka Semiconductor, Inc., Hsinchu, Taiwan
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2000 – 2009
- 2007
[j3]Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 767-776 (2007)- 2006
- [c4]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu:
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs. ITC 2006: 1-8 - 2005
- [c3]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
A Scan Matrix Design for Low Power Scan-Based Test. Asian Test Symposium 2005: 224-229 - [c2]Shih Ping Lin, Chung-Len Lee, Jwu E. Chen:
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. Asian Test Symposium 2005: 324-329 - 2004
- [j2]Yao-Wen Chang
, Shih-Ping Lin:
MR: a new framework for multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 793-800 (2004) - 2003
- [j1]Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin:
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 679-686 (2003) - 2002
- [c1]Shih-Ping Lin, Yao-Wen Chang:
A novel framework for multilevel routing considering routability and performance. ICCAD 2002: 44-50
Coauthor Index
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