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2010 – 2019
- 2017
[c10]Liu Liu
, Ping Chi, Shuangchen Li, Yuanqing Cheng, Yuan Xie:
Building energy-efficient multi-level cell STT-RAM caches with data compression. ASP-DAC 2017: 751-756- [c9]Hengyu Zhao, Linuo Xue, Ping Chi, Jishen Zhao:
Approximate image storage with multi-level cell STT-MRAM main memory. ICCAD 2017: 268-275 - 2016
- [b1]Ping Chi:
Facilitating Emerging Non-volatile Memories in Next-Generation Memory System Design: Architecture-Level and Application-Level Perspectives. University of California, Santa Barbara, USA, 2016 - [j3]Ping Chi, Wang-Chien Lee, Yuan Xie:
Adapting B+ -Tree for Emerging Nonvolatile Memory-Based Main Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1461-1474 (2016) - [c8]Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung-Hyuk Kang, Yuan Xie:
Architecture design with STT-RAM: Opportunities and challenges. ASP-DAC 2016: 109-114 - [c7]Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie:
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. ISCA 2016: 27-39 - [c6]Yu Ji, Youhui Zhang, Shuangchen Li, Ping Chi, Cihang Jiang, Peng Qu, Yuan Xie, Wenguang Chen:
NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints. MICRO 2016: 21:1-21:13 - 2015
- [j2]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. Inf. Media Technol. 10(2): 182-191 (2015) - [j1]Jishen Zhao, Cong Xu, Ping Chi, Yuan Xie:
Memory and Storage System Design with Nonvolatile Memory Technologies. IPSJ Trans. Syst. LSI Des. Methodol. 8: 2-11 (2015) - [c5]Shuangchen Li, Ping Chi, Jishen Zhao, Kwang-Ting Cheng, Yuan Xie:
Leveraging nonvolatility for architecture design with emerging NVM. NVMSA 2015: 1-5 - 2014
- [c4]Ping Chi, Cong Xu, Tao Zhang, Xiangyu Dong, Yuan Xie:
Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing. ICCAD 2014: 301-308 - [c3]Ping Chi, Wang-Chien Lee, Yuan Xie:
Making B+-tree efficient in PCM-based main memory. ISLPED 2014: 69-74 - [c2]Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie:
Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. ISQED 2014: 639-644 - 2010
- [c1]Shuhua Zhang, Weibei Dou, Ping Chi, Huazhong Yang:
MDCT spectrum separation: Catching the fine spectral structures for stereo coding. ICASSP 2010: 369-372
Coauthor Index
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