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ORCIDYuta Yamato
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2010 – 2019
- 2016
[j9]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. 99-D(10): 2591-2599 (2016)- [c20]Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte:
Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test. ATS 2016: 19-24 - [c19]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS 2016: 1-2 - 2015
- [c18]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato:
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS 2015: 1-6 - 2014
- [c17]Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS 2014: 292-297 - [c16]Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue:
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA 2014: 85-88 - 2013
- [j8]Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte:
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing. IEEE Des. Test 30(4): 60-70 (2013) - [j7]Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing. IEICE Trans. Inf. Syst. 96-D(9): 2003-2011 (2013) - 2012
- [c15]Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8 - [c14]Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara:
A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits. VTS 2012: 197-202 - 2011
- [j6]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(4): 833-840 (2011) - [j5]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing. IEICE Trans. Inf. Syst. 94-D(6): 1216-1226 (2011) - [c13]Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel:
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium 2011: 90-95 - [c12]Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara:
Transition-Time-Relation based capture-safety checking for at-speed scan test generation. DATE 2011: 895-898 - [c11]Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich:
SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures. ISLPED 2011: 33-38 - [c10]Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang:
A novel scan segmentation design method for avoiding shift timing failure in scan testing. ITC 2011: 1-8 - [c9]Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor:
Power-aware test generation with guaranteed launch safety for at-speed scan testing. VTS 2011: 166-171 - 2010
- [j4]Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme. IEICE Trans. Inf. Syst. 93-D(1): 2-9 (2010) - [j3]Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1309-1318 (2010)
2000 – 2009
- 2009
- [c8]Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa:
CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing. Asian Test Symposium 2009: 99-104 - [c7]Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara:
A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. ICCAD 2009: 97-104 - [c6]Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara:
A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing. PRDC 2009: 81-86 - 2008
- [j2]Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara:
A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits. IEICE Trans. Inf. Syst. 91-D(3): 667-674 (2008) - [c5]Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor:
CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing. ATS 2008: 397-402 - [c4]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS 2008: 55-60 - [c3]Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara:
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification. ICCAD 2008: 52-58 - 2007
- [c2]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang:
A novel scheme to reduce power supply noise for high-quality at-speed scan testing. ITC 2007: 1-10 - 2006
- [j1]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Trans. Inf. Syst. 89-D(11): 2756-2765 (2006) - [c1]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006: 251-258
Coauthor Index
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