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dblp: Ahmedullah Aziz https://dblp.org/pid/64/11473.html dblp person page RSS feed Mon, 07 Oct 2024 21:14:48 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Ahmedullah Azizhttps://dblp.org/pid/64/11473.html14451 Compact Model of a Topological Transistor.https://doi.org/10.1109/ACCESS.2024.3363645, , , :
Compact Model of a Topological Transistor. IEEE Access 12: 23200-23205 ()]]>https://dblp.org/rec/journals/access/0006AHA24Mon, 01 Jan 2024 00:00:00 +0100 CMOS-Based Single-Cycle in-Memory XOR/XNOR.https://doi.org/10.1109/ACCESS.2024.3384752, , , , :
CMOS-Based Single-Cycle in-Memory XOR/XNOR. IEEE Access 12: 49528-49534 ()]]>https://dblp.org/rec/journals/access/AlamHSAA24Mon, 01 Jan 2024 00:00:00 +0100 Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths.https://doi.org/10.1109/TCAD.2023.3299838, , , , , :
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(1): 151-160 ()]]>https://dblp.org/rec/journals/tcad/AlamHAIGA24Mon, 01 Jan 2024 00:00:00 +0100 Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance Computing.https://doi.org/10.1145/3649476.3660375, :
Ultra-Area-Efficient Cryogenic XNOR Logic Gate with Superconducting Heater Cryotron to Advance High-Performance Computing. ACM Great Lakes Symposium on VLSI : 651-656]]>https://dblp.org/rec/conf/glvlsi/AlamA24Mon, 01 Jan 2024 00:00:00 +0100 P-ReTI: Silicon Photonic Accelerator for Greener and Real-Time AI.https://doi.org/10.1145/3649476.3660376, , :
P-ReTI: Silicon Photonic Accelerator for Greener and Real-Time AI. ACM Great Lakes Symposium on VLSI : 766-769]]>https://dblp.org/rec/conf/glvlsi/DangDA24Mon, 01 Jan 2024 00:00:00 +0100 A SPICE-based Emulator Framework for Quantum Error Correction Circuits using LC Resonators.https://doi.org/10.1109/ISQED60706.2024.10528720, , :
A SPICE-based Emulator Framework for Quantum Error Correction Circuits using LC Resonators. ISQED : 1-5]]>https://dblp.org/rec/conf/isqed/IslamHA24Mon, 01 Jan 2024 00:00:00 +0100 Sub-Micron Binary HyperPixel Sensor Circuit: In-Pixel Binarization with Variable Thresholding.https://doi.org/10.1109/ISVLSI61997.2024.00016, , , :
Sub-Micron Binary HyperPixel Sensor Circuit: In-Pixel Binarization with Variable Thresholding. ISVLSI : 21-26]]>https://dblp.org/rec/conf/isvlsi/UdoyIJA24Mon, 01 Jan 2024 00:00:00 +0100 Quantum Anomalous Hall Effect Ternary Content Addressable Memory.https://doi.org/10.1109/ISVLSI61997.2024.00141, , , , :
Quantum Anomalous Hall Effect Ternary Content Addressable Memory. ISVLSI : 730-734]]>https://dblp.org/rec/conf/isvlsi/AshbachIAAG24Mon, 01 Jan 2024 00:00:00 +0100 A Review on Digital Pixel Sensors.https://doi.org/10.48550/arXiv.2402.04507, , , , :
A Review on Digital Pixel Sensors. CoRR abs/2402.04507 ()]]>https://dblp.org/rec/journals/corr/abs-2402-04507Mon, 01 Jan 2024 00:00:00 +0100 Harnessing Ferro-Valleytricity in Penta-Layer Rhombohedral Graphene for Memory and Compute.https://doi.org/10.48550/arXiv.2408.01028, , , , , :
Harnessing Ferro-Valleytricity in Penta-Layer Rhombohedral Graphene for Memory and Compute. CoRR abs/2408.01028 ()]]>https://dblp.org/rec/journals/corr/abs-2408-01028Mon, 01 Jan 2024 00:00:00 +0100 Cryogenic In-Memory Bit-Serial Addition Using Quantum Anomalous Hall Effect-Based Majority Logic.https://doi.org/10.1109/ACCESS.2023.3285604, , , , :
Cryogenic In-Memory Bit-Serial Addition Using Quantum Anomalous Hall Effect-Based Majority Logic. IEEE Access 11: 60717-60723 ()]]>https://dblp.org/rec/journals/access/AlamIHJA23Sun, 01 Jan 2023 00:00:00 +0100 Evaluating Neuron Models through Application-Hardware Co-Design.https://doi.org/10.1109/IEEECONF59524.2023.10477027, , , , :
Evaluating Neuron Models through Application-Hardware Co-Design. ACSSC : 537-542]]>https://dblp.org/rec/conf/acssc/SchumanDPAR23Sun, 01 Jan 2023 00:00:00 +0100 Cryogenic In-Memory Matrix-Vector Multiplication using Ferroelectric Superconducting Quantum Interference Device (FE-SQUID).https://doi.org/10.1109/DAC56929.2023.10247669, , , , , :
Cryogenic In-Memory Matrix-Vector Multiplication using Ferroelectric Superconducting Quantum Interference Device (FE-SQUID). DAC : 1-6]]>https://dblp.org/rec/conf/dac/AlamHHNNA23Sun, 01 Jan 2023 00:00:00 +0100 Reconfigurable Superconducting Logic Using Multi-Gate Switching of a Nano-Cryotron.https://doi.org/10.1109/DRC58590.2023.10186942, , :
Reconfigurable Superconducting Logic Using Multi-Gate Switching of a Nano-Cryotron. DRC : 1-2]]>https://dblp.org/rec/conf/drc/AlamMA23Sun, 01 Jan 2023 00:00:00 +0100 A Cryogenic Artificial Synapse based on Superconducting Memristor.https://doi.org/10.1145/3583781.3590203, , , , :
A Cryogenic Artificial Synapse based on Superconducting Memristor. ACM Great Lakes Symposium on VLSI : 143-148]]>https://dblp.org/rec/conf/glvlsi/IslamAUHA23Sun, 01 Jan 2023 00:00:00 +0100 Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories.https://doi.org/10.1145/3583781.3590236, , , , , :
Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories. ACM Great Lakes Symposium on VLSI : 521-526]]>https://dblp.org/rec/conf/glvlsi/GovindankuttyAD23Sun, 01 Jan 2023 00:00:00 +0100 Impact of Neuron Firing Rate on Application and Algorithm Performance.https://doi.org/10.1145/3589737.3605996, , , , :
Impact of Neuron Firing Rate on Application and Algorithm Performance. ICONS : 14:1-14:4]]>https://dblp.org/rec/conf/icons2/SharpeSIAS23Sun, 01 Jan 2023 00:00:00 +0100 A SPICE-based Framework to Emulate Quantum Circuits with classical LC Resonators.https://doi.org/10.1109/ISQED57927.2023.10129351, , :
A SPICE-based Framework to Emulate Quantum Circuits with classical LC Resonators. ISQED : 1-7]]>https://dblp.org/rec/conf/isqed/0006HA23Sun, 01 Jan 2023 00:00:00 +0100 A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths.https://doi.org/10.1109/ISQED57927.2023.10129314, , :
A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths. ISQED : 1-7]]>https://dblp.org/rec/conf/isqed/AlamAA23Sun, 01 Jan 2023 00:00:00 +0100 Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories.https://doi.org/10.1109/ISQED57927.2023.10129345, , , , :
Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories. ISQED : 1-7]]>https://dblp.org/rec/conf/isqed/GovindankuttyAD23Sun, 01 Jan 2023 00:00:00 +0100 Quantum Anomalous Hall Effect-Based Variation Robust Binary Content Addressable Memory.https://doi.org/10.1109/MWSCAS57524.2023.10406068, , , , , :
Quantum Anomalous Hall Effect-Based Variation Robust Binary Content Addressable Memory. MWSCAS : 331-335]]>https://dblp.org/rec/conf/mwscas/IslamHAHJA23Sun, 01 Jan 2023 00:00:00 +0100 Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories.https://doi.org/10.1109/VTS56346.2023.10140068, , , , , , , , :
Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories. VTS : 1-10]]>https://dblp.org/rec/conf/vts/YaylaTIWHAYCA23Sun, 01 Jan 2023 00:00:00 +0100 Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging.https://doi.org/10.48550/arXiv.2306.10244, , , , :
Superconducting Heater Cryotron-Based Reconfigurable Logic Towards Cryogenic IC Camouflaging. CoRR abs/2306.10244 ()]]>https://dblp.org/rec/journals/corr/abs-2306-10244Sun, 01 Jan 2023 00:00:00 +0100 A Deep Dive into the Design Space of a Dynamically Reconfigurable Cryogenic Spiking Neuron.https://doi.org/10.48550/arXiv.2308.15754, , , , :
A Deep Dive into the Design Space of a Dynamically Reconfigurable Cryogenic Spiking Neuron. CoRR abs/2308.15754 ()]]>https://dblp.org/rec/journals/corr/abs-2308-15754Sun, 01 Jan 2023 00:00:00 +0100 Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing.https://doi.org/10.48550/arXiv.2308.15756, , , , , , , :
Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing. CoRR abs/2308.15756 ()]]>https://dblp.org/rec/journals/corr/abs-2308-15756Sun, 01 Jan 2023 00:00:00 +0100 CMOS-based Single-Cycle In-Memory XOR/XNOR.https://doi.org/10.48550/arXiv.2310.18375, , , , :
CMOS-based Single-Cycle In-Memory XOR/XNOR. CoRR abs/2310.18375 ()]]>https://dblp.org/rec/journals/corr/abs-2310-18375Sun, 01 Jan 2023 00:00:00 +0100 Machine Learning-powered Compact Modeling of Stochastic Electronic Devices using Mixture Density Networks.https://doi.org/10.48550/arXiv.2311.05820, , , , , :
Machine Learning-powered Compact Modeling of Stochastic Electronic Devices using Mixture Density Networks. CoRR abs/2311.05820 ()]]>https://dblp.org/rec/journals/corr/abs-2311-05820Sun, 01 Jan 2023 00:00:00 +0100 A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices.https://doi.org/10.1109/ACCESS.2022.3218333, , , , , , :
A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices. IEEE Access 10: 115513-115519 ()]]>https://dblp.org/rec/journals/access/HutchinsAZBCRA22Sat, 01 Jan 2022 00:00:00 +0100 Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier.https://doi.org/10.1109/DRC55272.2022.9855654, , , :
Superconducting Josephson Junction FET-based Cryogenic Voltage Sense Amplifier. DRC : 1-2]]>https://dblp.org/rec/conf/drc/AlamIHA22Sat, 01 Jan 2022 00:00:00 +0100 Cryogenic Memory Array based on Ferroelectric SQUID and Heater Cryotron.https://doi.org/10.1109/DRC55272.2022.9855813, , , , , :
Cryogenic Memory Array based on Ferroelectric SQUID and Heater Cryotron. DRC : 1-2]]>https://dblp.org/rec/conf/drc/AlamIHNNA22Sat, 01 Jan 2022 00:00:00 +0100 Design Space Analysis of Superconducting Nanowire-based Cryogenic Oscillators.https://doi.org/10.1109/DRC55272.2022.9855804, , , :
Design Space Analysis of Superconducting Nanowire-based Cryogenic Oscillators. DRC : 1-2]]>https://dblp.org/rec/conf/drc/IslamASA22Sat, 01 Jan 2022 00:00:00 +0100 Variation-aware Design Space Exploration of Mott Memristor-based Neuristors.https://doi.org/10.1109/ISVLSI54635.2022.00025, , , , , :
Variation-aware Design Space Exploration of Mott Memristor-based Neuristors. ISVLSI : 68-73]]>https://dblp.org/rec/conf/isvlsi/AlamIJCRA22Sat, 01 Jan 2022 00:00:00 +0100 A Privacy-Protecting Framework of Autonomous Contact Tracing for SARS-CoV-2 and Beyond.https://arxiv.org/abs/2201.11796, , :
A Privacy-Protecting Framework of Autonomous Contact Tracing for SARS-CoV-2 and Beyond. CoRR abs/2201.11796 ()]]>https://dblp.org/rec/journals/corr/abs-2201-11796Sat, 01 Jan 2022 00:00:00 +0100 Cryogenic Neuromorphic Hardware.https://doi.org/10.48550/arXiv.2204.07503, , , , :
Cryogenic Neuromorphic Hardware. CoRR abs/2204.07503 ()]]>https://dblp.org/rec/journals/corr/abs-2204-07503Sat, 01 Jan 2022 00:00:00 +0100 CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays.https://doi.org/10.48550/arXiv.2205.14729, , , , , , , , , , :
CMOS-Compatible Ising Machines built using Bistable Latches Coupled through Ferroelectric Transistor Arrays. CoRR abs/2205.14729 ()]]>https://dblp.org/rec/journals/corr/abs-2205-14729Sat, 01 Jan 2022 00:00:00 +0100 Voltage-controlled Cryogenic Boolean Logic Family Based on Ferroelectric SQUID.https://doi.org/10.48550/arXiv.2212.08202, , , , :
Voltage-controlled Cryogenic Boolean Logic Family Based on Ferroelectric SQUID. CoRR abs/2212.08202 ()]]>https://dblp.org/rec/journals/corr/abs-2212-08202Sat, 01 Jan 2022 00:00:00 +0100 Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs.https://doi.org/10.1145/3453688.3461742, , , :
Monte Carlo Variation Analysis of NCFET-based 6-T SRAM: Design Opportunities and Trade-offs. ACM Great Lakes Symposium on VLSI : 467-472]]>https://dblp.org/rec/conf/glvlsi/AlamAGA21Fri, 01 Jan 2021 00:00:00 +0100 A Three-terminal Non-Volatile Ferroelectric Switch with an Insulator-Metal Transition Channel.https://arxiv.org/abs/2108.12091, , , , , :
A Three-terminal Non-Volatile Ferroelectric Switch with an Insulator-Metal Transition Channel. CoRR abs/2108.12091 ()]]>https://dblp.org/rec/journals/corr/abs-2108-12091Fri, 01 Jan 2021 00:00:00 +0100 An Oscillator-based MaxSAT solver.https://arxiv.org/abs/2109.09897, , , , , , , , , , :
An Oscillator-based MaxSAT solver. CoRR abs/2109.09897 ()]]>https://dblp.org/rec/journals/corr/abs-2109-09897Fri, 01 Jan 2021 00:00:00 +0100 Cryogenic Memory Technologies.https://arxiv.org/abs/2111.09436, , , :
Cryogenic Memory Technologies. CoRR abs/2111.09436 ()]]>https://dblp.org/rec/journals/corr/abs-2111-09436Fri, 01 Jan 2021 00:00:00 +0100 CryoCiM: Cryogenic Compute-in-Memory based on the Quantum Anomalous Hall Effect.https://arxiv.org/abs/2112.00124, , , , :
CryoCiM: Cryogenic Compute-in-Memory based on the Quantum Anomalous Hall Effect. CoRR abs/2112.00124 ()]]>https://dblp.org/rec/journals/corr/abs-2112-00124Fri, 01 Jan 2021 00:00:00 +0100 Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective.https://doi.org/10.1109/ISQED48828.2020.9136994, :
Insulator-Metal Transition Material Based Artificial Neurons: A Design Perspective. ISQED : 444-451]]>https://dblp.org/rec/conf/isqed/AzizR20Wed, 01 Jan 2020 00:00:00 +0100 A Non-Volatile Cryogenic Random-Access Memory Based on the Quantum Anomalous Hall Effect.https://arxiv.org/abs/2011.00170, , :
A Non-Volatile Cryogenic Random-Access Memory Based on the Quantum Anomalous Hall Effect. CoRR abs/2011.00170 ()]]>https://dblp.org/rec/journals/corr/abs-2011-00170Wed, 01 Jan 2020 00:00:00 +0100 Symmetric 2-D-Memory Access to Multidimensional Data.http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2801302, , , , , , , , , :
Symmetric 2-D-Memory Access to Multidimensional Data. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1040-1050 ()]]>https://dblp.org/rec/journals/tvlsi/GeorgeLLMSMASGN18Mon, 01 Jan 2018 00:00:00 +0100 Computing with ferroelectric FETs: Devices, models, systems, and applications.https://doi.org/10.23919/DATE.2018.8342213, , , , , , , , , , , , , , , , , , :
Computing with ferroelectric FETs: Devices, models, systems, and applications. DATE : 1289-1298]]>https://dblp.org/rec/conf/date/AzizBCCDGHHIJMM18Mon, 01 Jan 2018 00:00:00 +0100 A Three-Terminal Edge-Triggered Mott Switch.https://doi.org/10.1109/DRC.2018.8442274, , , :
A Three-Terminal Edge-Triggered Mott Switch. DRC : 1-2]]>https://dblp.org/rec/conf/drc/AzizEGS18Mon, 01 Jan 2018 00:00:00 +0100 Cockcroft-Walton Multiplier based on Unipolar Ag/HfO2/Pt Threshold Switch.https://doi.org/10.1109/DRC.2018.8442270, , , , :
Cockcroft-Walton Multiplier based on Unipolar Ag/HfO2/Pt Threshold Switch. DRC : 1-2]]>https://dblp.org/rec/conf/drc/AzizSSDG18Mon, 01 Jan 2018 00:00:00 +0100 Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.https://doi.org/10.1109/TCSI.2017.2702741, , , , , , , , , , :
Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(11): 2907-2919 ()]]>https://dblp.org/rec/journals/tcas/LiGMTASGCLDN17Sun, 01 Jan 2017 00:00:00 +0100 Harnessing ferroelectrics for non-volatile memories and logic.https://doi.org/10.1109/ISQED.2017.7918288, , , , , , :
Harnessing ferroelectrics for non-volatile memories and logic. ISQED : 29-34]]>https://dblp.org/rec/conf/isqed/GuptaWGALDN17Sun, 01 Jan 2017 00:00:00 +0100 Read-enhanced spin memories augmented by phase transition materials (Invited).https://doi.org/10.1109/MWSCAS.2017.8053093, :
Read-enhanced spin memories augmented by phase transition materials (Invited). MWSCAS : 993-996]]>https://dblp.org/rec/conf/mwscas/AzizG17Sun, 01 Jan 2017 00:00:00 +0100 Analysis of Functional Oxide based Selectors for Cross-Point Memories.https://doi.org/10.1109/TCSI.2016.2620475, , , :
Analysis of Functional Oxide based Selectors for Cross-Point Memories. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2222-2235 ()]]>https://dblp.org/rec/journals/tcas/AzizJDG16Fri, 01 Jan 2016 00:00:00 +0100 Nonvolatile memory design based on ferroelectric FETs.https://doi.org/10.1145/2897937.2898050, , , , , , , , , , :
Nonvolatile memory design based on ferroelectric FETs. DAC : 118:1-118:6]]>https://dblp.org/rec/conf/dac/GeorgeMALKSCDSG16Fri, 01 Jan 2016 00:00:00 +0100 Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.https://doi.org/10.1145/2966986.2967037, , , , , , :
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits. ICCAD : 121]]>https://dblp.org/rec/conf/iccad/YinANDGNH16Fri, 01 Jan 2016 00:00:00 +0100 On the potential of correlated materials in the design of spin-based cross-point memories (Invited).https://doi.org/10.1109/ISCAS.2016.7527451, , , :
On the potential of correlated materials in the design of spin-based cross-point memories (Invited). ISCAS : 1158-1161]]>https://dblp.org/rec/conf/iscas/GuptaASD16Fri, 01 Jan 2016 00:00:00 +0100 Ferroelectric Transistor based Non-Volatile Flip-Flop.https://doi.org/10.1145/2934583.2934603, , , , , :
Ferroelectric Transistor based Non-Volatile Flip-Flop. ISLPED : 10-15]]>https://dblp.org/rec/conf/islped/WangGADNG16Fri, 01 Jan 2016 00:00:00 +0100 Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors.https://doi.org/10.1109/ISVLSI.2016.116, , , , , , , :
Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors. ISVLSI : 649-654]]>https://dblp.org/rec/conf/isvlsi/GeorgeALKDSGN16Fri, 01 Jan 2016 00:00:00 +0100 COAST: Correlated material assisted STT MRAMs for optimized read operation.https://doi.org/10.1109/ISLPED.2015.7273481, , , :
COAST: Correlated material assisted STT MRAMs for optimized read operation. ISLPED : 1-6]]>https://dblp.org/rec/conf/islped/AzizSDG15Thu, 01 Jan 2015 00:00:00 +0100 Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.https://doi.org/10.1109/ISVLSI.2015.52, , , , , :
Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective. ISVLSI : 333-338]]>https://dblp.org/rec/conf/isvlsi/AzizCKDNG15Thu, 01 Jan 2015 00:00:00 +0100 Inherent Inter-vehicle Signaling Using Radio Frequency and Infra-red Communication.https://doi.org/10.1109/UKSim.2012.38, :
Inherent Inter-vehicle Signaling Using Radio Frequency and Infra-red Communication. UKSim : 211-215]]>https://dblp.org/rec/conf/uksim/AzizH12Sun, 01 Jan 2012 00:00:00 +0100 Design and Development of an Y4 Copter Control System.https://doi.org/10.1109/UKSim.2012.43, , , , , , :
Design and Development of an Y4 Copter Control System. UKSim : 251-256]]>https://dblp.org/rec/conf/uksim/HossainKMAHIS12Sun, 01 Jan 2012 00:00:00 +0100