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ORCIDJosé Alberto Espejo
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2000 – 2009
- 2008
[c9]Enrique San Millán, Luis Entrena
, José Alberto Espejo:
Logic Transformations by Multiple Wire Network Addition. DSD 2008: 779-786- 2003
- [j1]Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López:
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. J. Syst. Archit. 49(12-15): 529-541 (2003) - 2001
- [c8]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472 - [c7]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397 - [c6]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299 - [c5]Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94 - [c4]Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo:
Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
1990 – 1999
- 1999
- [c3]Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno:
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520 - [c2]José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías:
Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161- - 1996
- [c1]Luis Entrena, Emilio Olías, Javier Uceda, José Alberto Espejo:
Timing optimization by an improved redundancy addition and removal technique. EURO-DAC 1996: 342-347
Coauthor Index
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