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2020 – today
- 2023
[c19]Yun-Nan Chang:
Design of Low-cost IOU Circuit for Post-processing of Object Detection. GCCE 2023: 407-408
2010 – 2019
- 2019
- [c18]Yun-Nan Chang, Guan-Jhen Chen:
Design of A Bit-Serial Artificial Neuron VLSI Architecture with Early Termination. ICEIC 2019: 1-3 - [c17]Yun-Nan Chang, Yu-Tang Tin:
Scaling Bit-Flexible Neural Networks. ISOCC 2019: 253-254 - 2017
- [c16]Yun-Nan Chang, Chin-Lun Yang:
A fast ray tracing scheme for dynamic scenes. CoDIT 2017: 872-875 - 2016
- [c15]Yun-Nan Chang:
Design of an area-efficient partial-sum architecture for polar decoders based on new matrix generator. NEWCAS 2016: 1-4 - 2015
- [j12]Yun-Nan Chang, Ting-Chi Tong:
An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering. J. Signal Process. Syst. 79(1): 63-74 (2015) - [c14]Hsu-Kang Dow
, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee:
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT 2015: 1-4 - 2014
- [c13]Yun-Nan Chang, Ting-Chi Tong:
Design of a 2D graphics front-end rendering processor. ASAP 2014: 70-71 - 2013
- [j11]Ting-Chi Tong, Yun-Nan Chang:
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer. IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1246-1259 (2013) - [c12]Yun-Nan Chang, Keshab K. Parhi:
Architectures for digital filters using stochastic computing. ICASSP 2013: 2697-2701 - [c11]Yun-Nan Chang:
Two-level hierarchical fill-buffer for graphics rendering systems. NEWCAS 2013: 1-4 - 2010
- [j10]Yun-Nan Chang:
A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 840-843 (2010) - [j9]Yun-Nan Chang:
Digit-Serial Pipeline Sorter Architecture. J. Signal Process. Syst. 61(2): 241-249 (2010)
2000 – 2009
- 2009
- [j8]Yun-Nan Chang:
A Fast Spline Curve Rendering Accelerator Architecture. IEEE Trans. Circuits Syst. II Express Briefs 56-II(11): 870-874 (2009) - [c10]Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC 2009: 131-132 - [c9]Yun-Nan Chang, Ting-Chi Tong:
A Lossless Buffer Compression Scheme for 3D Graphic System. CGVR 2009: 116-121 - 2008
- [j7]Yun-Nan Chang:
An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design. IEEE Trans. Circuits Syst. II Express Briefs 55-II(12): 1234-1238 (2008) - [j6]Yun-Nan Chang:
A low-cost dual-mode deinterleaver design. IEEE Trans. Consumer Electron. 54(2): 326-332 (2008) - [j5]Yun-Nan Chang, Ting-Chi Tong:
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization. J. Signal Process. Syst. 53(3): 435-448 (2008) - 2005
- [c8]Yun-Nan Chang:
Design of an efficient memory-based DVB-T channel decoder. ISCAS (5) 2005: 5019-5022 - 2003
- [j4]Yun-Nan Chang, Keshab K. Parhi:
An efficient pipelined FFT architecture. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 322-325 (2003) - [j3]Yun-Nan Chang:
An Efficient In-Place VLSI Architecture for Viterbi Algorithm. J. VLSI Signal Process. 33(3): 317-324 (2003) - [c7]Yun-Nan Chang:
Design of soft-output Viterbi decoders with hybrid trace-back processing. ISCAS (2) 2003: 69-72 - 2000
- [j2]Yun-Nan Chang, Hiroshi Suzuki, Keshab K. Parhi:
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder. IEEE J. Solid State Circuits 35(6): 826-834 (2000)
1990 – 1999
- 1999
- [c6]Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi:
Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems. CICC 1999: 589-592 - [c5]Hiroshi Suzuki, Yun-Nan Chang, Keshab K. Parhi:
Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems. ICASSP 1999: 1913-1916 - 1998
- [j1]Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi:
Heuristic Loop-Based Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units. J. VLSI Signal Process. 19(3): 243-256 (1998) - [c4]Yun-Nan Chang, Keshab K. Parhi:
High-performance digit-serial complex-number multiplier-accumulator. ICCD 1998: 211-213 - 1997
- [c3]Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi:
Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD 1997: 186-195 - 1996
- [c2]Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi:
Loop-List Scheduling for Heterogeneous Functional Units. Great Lakes Symposium on VLSI 1996: 2-7 - [c1]Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang:
Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. ICCD 1996: 492-499
Coauthor Index
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