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2010 – 2019
- 2017
[j19]Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue:
An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan. IEICE Trans. Inf. Syst. 100-D(1): 130-139 (2017)- [j18]Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue:
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell. Integr. 57: 108-124 (2017) - [c38]Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani
, Michiko Inoue, Alex Orailoglu:
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS 2017: 52-57 - [c37]Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu:
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions. ETS 2017: 1-6 - 2016
- [j17]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair. IEICE Trans. Inf. Syst. 99-D(10): 2591-2599 (2016) - [c36]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue:
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC. ETS 2016: 1-2 - 2015
- [c35]Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato:
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement. ETS 2015: 1-6 - 2014
- [c34]Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units. ATS 2014: 292-297 - [c33]Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue:
Memory block based scan-BIST architecture for application-dependent FPGA testing. FPGA 2014: 85-88 - 2012
- [j16]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara:
Test Pattern Ordering and Selection for High Quality Test Set under Constraints. IEICE Trans. Inf. Syst. 95-D(12): 3001-3009 (2012) - [j15]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
A Failure Prediction Strategy for Transistor Aging. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1951-1959 (2012) - [c32]Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura:
DART: Dependable VLSI test architecture and its implementation. ITC 2012: 1-10 - [c31]Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue:
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation. ITC 2012: 1-8 - 2011
- [j14]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J. Electron. Test. 27(2): 99-108 (2011) - [j13]Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda:
Delay Testing: Improving Test Quality and Avoiding Over-testing. Inf. Media Technol. 6(4): 1053-1066 (2011) - [j12]Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda:
Delay Testing: Improving Test Quality and Avoiding Over-testing. IPSJ Trans. Syst. LSI Des. Methodol. 4: 117-130 (2011) - [c30]Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Temperature-Variation-Aware Test Pattern Optimization. ETS 2011: 214 - [c29]Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara:
Faster-than-at-speed test for increased test quality and in-field reliability. ITC 2011: 1-9 - 2010
- [j11]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. 93-D(6): 1549-1559 (2010) - [c28]Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara:
RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. APCCAS 2010: 264-267 - [c27]Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara:
Seed Ordering and Selection for High Quality Delay Test. Asian Test Symposium 2010: 313-318 - [c26]Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara:
Test pattern selection to optimize delay test quality with a limited size of test set. ETS 2010: 260 - [c25]Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara:
Aging test strategy and adaptive test scheduling for SoC failure prediction. IOLTS 2010: 21-26 - [c24]Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara:
Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. VTS 2010: 188-193
2000 – 2009
- 2009
- [c23]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. ASP-DAC 2009: 793-798 - [c22]Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara:
Partial Scan Approach for Secret Information Protection. ETS 2009: 143-148 - 2008
- [j10]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Scheduling Power-Constrained Tests through the SoC Functional Bus. IEICE Trans. Inf. Syst. 91-D(3): 736-746 (2008) - [j9]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. IEICE Trans. Inf. Syst. 91-D(3): 747-755 (2008) - [j8]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. IEICE Trans. Inf. Syst. 91-D(3): 807-814 (2008) - [j7]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. IEICE Trans. Inf. Syst. 91-D(7): 1999-2007 (2008) - [j6]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. IEICE Trans. Inf. Syst. 91-D(7): 2008-2017 (2008) - [j5]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. IEICE Trans. Inf. Syst. 91-D(10): 2440-2448 (2008) - [j4]Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1535-1544 (2008) - [c21]Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. ATS 2008: 125-130 - [c20]Tomokazu Yoneda, Hideo Fujiwara:
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. DATE 2008: 1366-1369 - 2007
- [c19]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. ASP-DAC 2007: 720-725 - [c18]Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. ATS 2007: 187-192 - [c17]Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara:
Test Scheduling for Memory Cores with Built-In Self-Repair. ATS 2007: 199-206 - [c16]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. ATS 2007: 459-462 - [c15]Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Time Expansion Model at Register Transfer Level. DAC 2007: 682-687 - [c14]Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara:
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. DATE 2007: 231-236 - [c13]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara:
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. ETS 2007: 35-42 - [c12]Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara:
Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. ISCAS 2007: 2942-2945 - [c11]Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara:
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. VTS 2007: 369-374 - [c10]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388 - 2006
- [j3]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. IEICE Trans. Inf. Syst. 89-D(4): 1490-1497 (2006) - [j2]Tomokazu Yoneda, Hideo Fujiwara:
Design for consecutive transparency method of RTL circuits. Syst. Comput. Jpn. 37(2): 1-10 (2006) - [c9]Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara:
A memory grouping method for sharing memory BIST logic. ASP-DAC 2006: 671-676 - [c8]Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara:
Power-constrained test scheduling for multi-clock domain SoCs. DATE 2006: 297-302 - [c7]Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara:
Power-Constrained SOC Test Schedules through Utilization of Functional Buses. ICCD 2006: 230-236 - 2005
- [c6]Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara:
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. Asian Test Symposium 2005: 150-155 - [c5]Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara:
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. Asian Test Symposium 2005: 306-311 - 2004
- [c4]Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard:
An efficient scan tree design for test time reduction. ETS 2004: 174-179 - 2003
- [c3]Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara:
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. ITC 2003: 415-422 - [c2]Tomokazu Yoneda, Hideo Fujiwara:
Design for Consecutive Transparency of Cores in System-on-a-Chip. VTS 2003: 287-292 - 2002
- [j1]Tomokazu Yoneda, Hideo Fujiwara:
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. J. Electron. Test. 18(4-5): 487-501 (2002) - 2001
- [c1]Tomokazu Yoneda, Hideo Fujiwara:
A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. Asian Test Symposium 2001: 193-198
Coauthor Index
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