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dblp: Chuan-pei Xu https://dblp.org/pid/55/7808.html dblp person page RSS feed Thu, 25 Apr 2024 05:59:25 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Chuan-pei Xuhttps://dblp.org/pid/55/7808.html14451 Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm.https://doi.org/10.1007/s12065-020-00513-6, , , , :
Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm. Evol. Intell. 15(1): 369-379 ()]]>https://dblp.org/rec/journals/evi/ZhouHZXW22Sat, 01 Jan 2022 00:00:00 +0100 On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure.https://doi.org/10.1007/s10836-020-05923-z, , :
On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure. J. Electron. Test. 37(1): 97-107 ()]]>https://dblp.org/rec/journals/et/HuangXZ21Fri, 01 Jan 2021 00:00:00 +0100 An Efficient Algorithm for Optimizing the Test Path of Digital Microfluidic Biochips.https://doi.org/10.1007/s10836-020-05865-6, , :
An Efficient Algorithm for Optimizing the Test Path of Digital Microfluidic Biochips. J. Electron. Test. 36(2): 205-218 ()]]>https://dblp.org/rec/journals/et/HuangXZ20Wed, 01 Jan 2020 00:00:00 +0100 A Fault Check Graph Approach for Photonic Router in Network on Chip.https://doi.org/10.1109/ATS.2018.00014, , , , :
A Fault Check Graph Approach for Photonic Router in Network on Chip. ATS : 13-18]]>https://dblp.org/rec/conf/ats/ZhuCXHS18Mon, 01 Jan 2018 00:00:00 +0100 Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks.https://doi.org/10.1007/s10836-016-5565-5, , , :
Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks. J. Electron. Test. 32(1): 31-42 ()]]>https://dblp.org/rec/journals/et/HuLXJ16Fri, 01 Jan 2016 00:00:00 +0100 Test scheduling with bandwidth division multiplexed for network-on-chip using refined quantum-inspired evolutionary algorithm.https://doi.org/10.3233/JCM-160702, , , , :
Test scheduling with bandwidth division multiplexed for network-on-chip using refined quantum-inspired evolutionary algorithm. J. Comput. Methods Sci. Eng. 16(4): 927-941 ()]]>https://dblp.org/rec/journals/jcmse/HuLXZJ16Fri, 01 Jan 2016 00:00:00 +0100 TAM/wrapper Co-optimization And Test Scheduling For SOCs Based On Hybrid Genetic Algorithm.http://www.jcomputers.us/index.php?m=content&c=index&a=show&catid=131&id=2061, , :
TAM/wrapper Co-optimization And Test Scheduling For SOCs Based On Hybrid Genetic Algorithm. J. Comput. 5(7): 1086-1093 ()]]>https://dblp.org/rec/journals/jcp/XuLH10Fri, 01 Jan 2010 00:00:00 +0100 A Technique for NoC Routing Based on Hybrid Particle Swarm Optimization Algorithm.https://doi.org/10.1109/WGEC.2009.42, , :
A Technique for NoC Routing Based on Hybrid Particle Swarm Optimization Algorithm. WGEC : 607-610]]>https://dblp.org/rec/conf/wgec/XuYC09Thu, 01 Jan 2009 00:00:00 +0100 Test Scheduling of SOC with Power Constraint Based on Particle Swarm Optimization Algorithm.https://doi.org/10.1109/WGEC.2009.61, , :
Test Scheduling of SOC with Power Constraint Based on Particle Swarm Optimization Algorithm. WGEC : 611-614]]>https://dblp.org/rec/conf/wgec/XuHN09Thu, 01 Jan 2009 00:00:00 +0100 Study on Test Generation of Sequential Circuits Based on Particle Swarm Optimization and Ant Algorithm.https://doi.org/10.1109/CSSE.2008.953, :
Study on Test Generation of Sequential Circuits Based on Particle Swarm Optimization and Ant Algorithm. CSSE (1) : 149-152]]>https://dblp.org/rec/conf/csse/JianC08Tue, 01 Jan 2008 00:00:00 +0100