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ORCIDWei Cao 0002
Person information
- affiliation: Fudan University, State Key Laboratory of ASIC and System, Shanghai, China
Other persons with the same name
- Wei Cao — disambiguation page
- Wei Cao 0001 — National University of Singapore, Department of Electrical and Computer Engineering, Singapore
- Wei Cao 0003
![[0000-0003-2663-758X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-2663-758X")
— University of Electronic Science and Technology of China, National Key Laboratory of Communications, Chengdu, China - Wei Cao 0004 — Ningbo University, Department of Mathematics, China
- Wei Cao 0005 — Sun Yat-Sen University, Planetary Environmental and Astrobiological Laboratory, School of Atmospheric Sciences, Zhuhai, China (and 2 more)
- Wei Cao 0006 — Alibaba Group, Alibaba Cloud Computing Ltd, Hangzhou, China (and 1 more)
Other persons with a similar name
- Qing-wei Cao
- Wei-Dong Cao
- Wei-Feng Cao
- Wei-Ping Cao
- Wei-Ting Cao
- Wei Hang Cao
- Wei Ping Cao
- Weihua Cao (aka: Wei-Hua Cao) — disambiguation page
- Zhi-Wei Cao (aka: Zhi Wei Cao, Zhiwei Cao)
- Cao Wei
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2020 – today
- 2024
[i1]Jialin Chen, Zhiqiang Cai, Ke Xu, Di Wu, Wei Cao:
Qubit-Wise Architecture Search Method for Variational Quantum Circuits. CoRR abs/2403.04268 (2024)- 2023
- [c24]Tianyang Li, Fan Zhang, Xitian Fan, Jianliang Shen, Wei Guo, Wei Cao:
Unified Accelerator for Attention and Convolution in Inference Based on FPGA. ISCAS 2023: 1-5 - 2022
- [j7]Xitian Fan, Guangwei Xie, Zhongcheng Huang, Wei Cao, Lingli Wang:
Acceleration of Rotated Object Detection on FPGA. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2296-2300 (2022) - 2021
- [j6]Siyu Xiong, Guoqing Wu, Xitian Fan, Xuan Feng, Zhongcheng Huang, Wei Cao, Xuegong Zhou, Shijin Ding, Jinhua Yu, Lingli Wang, Zhifeng Shi:
MRI-based brain tumor segmentation using FPGA-accelerated neural network. BMC Bioinform. 22(1): 421 (2021) - [j5]Di Wu, Xitian Fan, Wei Cao, Lingli Wang:
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 936-949 (2021) - [c23]Xuan Feng, Yue Li, Yu Qian, Jingbo Gao, Wei Cao, Lingli Wang:
A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions. FPT 2021: 1-4 - [c22]Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang:
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA. FPT 2021: 1-9 - 2020
- [c21]Yue Li, Wei Cao, Xuegong Zhou, Lingli Wang:
A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications. FPT 2020: 35-38
2010 – 2019
- 2019
- [j4]Cheng Luo, Wei Cao, Lingli Wang, Philip H. W. Leong:
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. IEICE Trans. Inf. Syst. 102-D(5): 1037-1045 (2019) - [c20]Mingjun Jiao, Yue Li, Pengbo Dang, Wei Cao, Lingli Wang:
A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System. FPT 2019: 215-223 - [c19]Di Wu, Wei Cao, Lingli Wang:
SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs. FPT 2019: 255-258 - 2018
- [j3]Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang:
Stream Processing Dual-Track CGRA for Object Inference. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1098-1111 (2018) - [c18]Cheng Luo, Yuhua Wang, Wei Cao, Philip H. W. Leong, Lingli Wang:
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks. FPL 2018: 60-63 - [c17]Di Wu, Jin Chen, Wei Cao, Lingli Wang:
A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture. FPL 2018: 64-67 - [c16]Liang Xie, Xitian Fan, Wei Cao, Lingli Wang:
High Throughput CNN Accelerator Design Based on FPGA. FPT 2018: 274-277 - 2017
- [c15]Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang:
Accelerating low bit-width convolutional neural networks with embedded FPGA. FPL 2017: 1-4 - 2016
- [c14]Xitian Fan, Huimin Li, Wei Cao, Lingli Wang:
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. FPL 2016: 1-9 - [c13]Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
A high performance FPGA-based accelerator for large-scale convolutional neural networks. FPL 2016: 1-9 - [c12]Qi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
High performance Deformable Part Model accelerator based on FPGA. FPT 2016: 245-248 - 2015
- [c11]Yangjie Zhang, Wei Cao, Lingli Wang:
Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA. ASICON 2015: 1-4 - 2013
- [c10]Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao:
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. ASICON 2013: 1-4 - [c9]Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan:
A reconfigurable floating-point FFT architecture. ASICON 2013: 1-4 - [c8]Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang:
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA. FPT 2013: 152-159 - [c7]Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang:
A hardware implementation of Bag of Words and Simhash for image recognition. FPT 2013: 418-421 - [c6]Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang:
An FPGA-cluster-accelerated match engine for content-based image retrieval. FPT 2013: 422-425 - 2011
- [j2]Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong:
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design. IEEE Trans. Circuits Syst. II Express Briefs 58-II(7): 432-436 (2011) - [c5]Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong:
A coarse-grained reconfigurable computing unit. ASICON 2011: 87-90 - [c4]Shuai Chen, Jialin Chen, Kanwen Wang, Wei Cao, Lingli Wang:
A permutation network for configurable and scalable FFT processors. ASICON 2011: 787-790
2000 – 2009
- 2008
- [j1]Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min:
A high-performance reconfigurable VLSI architecture for vbsme in H.264. IEEE Trans. Consumer Electron. 54(3): 1338-1345 (2008) - [c3]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A novel dynamic reconfigurable VLSI architecture for H.264 transforms. APCCAS 2008: 1810-1813 - [c2]Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong:
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform. ICECS 2008: 486-489 - [c1]Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min:
A high-performance reconfigurable 2-D transform architecture for H.264. ICECS 2008: 606-609
Coauthor Index
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