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ORCIDDinesh Somasekhar
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2010 – 2019
- 2016
[j19]Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li:
Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 105-108 (2016)- [j18]Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li:
Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 261-264 (2016) - [j17]Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park
, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar:
Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 265-278 (2016) - [j16]Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim:
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3468-3476 (2016) - 2014
- [j15]Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury:
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. IEEE J. Solid State Circuits 49(11): 2684-2693 (2014) - [c19]Toshiaki Kirihata, Dinesh Somasekhar:
Advanced memory topics. CICC 2014: 1 - 2012
- [j14]Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Direct Compare of Information Coded With Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2147-2151 (2012) - [c18]Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De:
A fully-digital phase-locked low dropout regulator in 32nm CMOS. VLSIC 2012: 148-149 - 2011
- [j13]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. IET Comput. Digit. Tech. 5(3): 205-212 (2011) - [c17]Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar:
3DICs for tera-scale computing: a case study. ISPD 2011: 77-78 - 2010
- [j12]Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang:
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. IEEE J. Solid State Circuits 45(4): 751-758 (2010) - [c16]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c15]Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Reducing cache power with low-cost, multi-bit error-correcting codes. ISCA 2010: 83-93
2000 – 2009
- 2009
- [j11]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi:
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44(1): 174-185 (2009) - [j10]Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De:
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44(4): 1199-1208 (2009) - 2008
- [c14]Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi:
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC 2008: 274-275 - 2007
- [j9]Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [c13]Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy:
Fine-Grained Redundancy in Adders. ISQED 2007: 317-321 - [c12]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2006
- [c11]Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De:
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS 2006 - [c10]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - 2005
- [c9]Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De:
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC 2005: 355-358 - 2003
- [j8]Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De:
A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38(5): 839-842 (2003) - [c8]Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson:
Bitline leakage equalization for sub-100nm caches. ESSCIRC 2003: 401-404 - 2002
- [j7]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002) - [j6]Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy:
Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 1-5 (2002) - [j5]Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy:
Skewed CMOS: noise-tolerant high-performance low-power static circuit family. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 469-476 (2002) - 2000
- [c7]Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De:
Dynamic noise analysis in precharge-evaluate circuits. DAC 2000: 243 - [c6]Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh, Dinesh Somasekhar:
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family. ICCD 2000: 241-246
1990 – 1999
- 1999
- [j4]Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(6): 714-725 (1999) - [c5]Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy:
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC 1999: 442-445 - [c4]Khurram Muhammad, Dinesh Somasekhar, Kaushik Roy:
Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design. ICCD 1999: 230-235 - 1998
- [j3]Dinesh Somasekhar, Kaushik Roy:
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 573-577 (1998) - [c3]Hendrawan Soeleman, Dinesh Somasekhar, Kaushik Roy:
IDD Waveforms Analysis for Testing of Domino and Low Voltage Static CMOS Circuits. Great Lakes Symposium on VLSI 1998: 243-248 - 1997
- [c2]Dinesh Somasekhar, Kaushik Roy:
LVDCSL: low voltage differential current switch logic, a robust low power DCSL family. ISLPED 1997: 18-23 - 1996
- [j2]Dinesh Somasekhar, Kaushik Roy:
Differential current switch logic: a low power DCVS logic family. IEEE J. Solid State Circuits 31(7): 981-991 (1996) - 1993
- [j1]Dinesh Somasekhar, V. Visvanathan:
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 415-422 (1993) - [c1]Dinesh Somasekhar, V. Visvanathan:
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design 1993: 347-350
Coauthor Index
aka: Vivek K. De
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