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ORCIDRajeev Jain
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[c31]Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang:
DE-HNN: An effective neural model for Circuit Netlist representation. AISTATS 2024: 4258-4266- [c30]Chenhui Deng
, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang:
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. DAC 2024: 175:1-175:6 - [i5]Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang:
Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. CoRR abs/2403.01317 (2024) - [i4]Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Donghyeon Koh, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang:
DE-HNN: An effective neural model for Circuit Netlist representation. CoRR abs/2404.00477 (2024) - 2023
- [c29]Justin M. Wozniak, Rajeev Jain, Andreas Wilke, Rylie Weaver, Alexander Partin, Thomas S. Brettin, Rick Stevens:
An Automation Framework for Comparison of Cancer Response Models Across Configurations. e-Science 2023: 1-10 - [i3]Akash Dhruv, Rajeev Jain, Jared O'Neal, Klaus Weide, Anshu Dubey:
Framework and Methodology for Verification of a Complex Scientific Simulation Software, Flash-X. CoRR abs/2308.16180 (2023) - 2022
- [j21]James Austin Harris, Ran Chu, Sean M. Couch, Anshu Dubey, Eirik Endeve, Antigoni Georgiadou, Rajeev Jain, Daniel Kasen, M. Paul Laiu, O. E. Bronson Messer, Jared O'Neal, Michael A. Sandoval, Klaus Weide:
Exascale models of stellar explosions: Quintessential multi-physics simulation. Int. J. High Perform. Comput. Appl. 36(1): 59-77 (2022) - [j20]Anshu Dubey, Klaus Weide, Jared O'Neal, Akash Dhruv, Sean M. Couch, James Austin Harris, Tom Klosterman, Rajeev Jain, Johann Rudi, Bronson Messer, Michael Pajkos, Jared Carlson, Ran Chu, Mohamed Wahib, Saurabh Chawdhary, Paul M. Ricker, Dongwook Lee, Katie Antypas, Katherine M. Riley, Christopher S. Daley, Murali K. Ganapathy, Francis X. Timmes, Dean M. Townsley, Marcos Vanella, John Bachan, Paul M. Rich, Shravan Kumar, Eirik Endeve, W. Raphael Hix, Anthony Mezzacappa, Thomas Papatheodore:
Flash-X: A multiphysics simulation software instrument. SoftwareX 19: 101168 (2022) - [j19]Keertana Settaluri, Zhaokai Liu, Rishubh Khurana, Arash Mirhaj, Rajeev Jain, Borivoje Nikolic:
Automated Design of Analog Circuits Using Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2794-2807 (2022) - [c28]Rajeev Jain, Houjun Tang, Akash Dhruv, James Austin Harris, Suren Byna:
Accelerating Flash-X Simulations with Asynchronous I/O. PDSW@SC 2022: 13-19 - [c27]Christopher Patrick, S. C. Song, Irfan Khan, Nader Nikfar, Matt Severson, Shree Pandey, Matt Kaiser, Manav Shah, Pat Lawlor, Deb Marich, Carina Affinito, Rajeev Jain:
From System-on-Chip (SoC) to System on Multi-Chip (SoMC) architectures: Scaling integrated systems beyond the limitations of deep-submicron single chip technologies. VLSI Technology and Circuits 2022: 1-2 - [i2]Anshu Dubey, Klaus Weide, Jared O'Neal, Akash Dhruv, Sean M. Couch, James Austin Harris, Tom Klosterman, Rajeev Jain, Johann Rudi, Bronson Messer, Michael Pajkos, Jared Carlson, Ran Chu, Mohamed Wahib, Saurabh Chawdhary, Paul M. Ricker, Dongwook Lee, Katie Antypas, Katherine M. Riley, Christopher S. Daley, Murali K. Ganapathy, Francis X. Timmes, Dean M. Townsley, Marcos Vanella, John Bachan, Paul Rich, Shravan Kumar, Eirik Endeve, W. Raphael Hix, Anthony Mezzacappa, Thomas Papatheodore:
Flash-X, a multiphysics simulation software instrument. CoRR abs/2208.11630 (2022) - 2021
- [c26]W. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain:
Fast and Accurate PPA Modeling with Transfer Learning. ICCAD 2021: 1-8 - [i1]Rajeev Jain, Klaus Weide, Saurabh Chawdhary, Thomas Klostermann:
Checkpoint/Restart for Lagrangian particle mesh with AMR in community code FLASH-X. CoRR abs/2103.04267 (2021) - 2020
- [c25]Rajeev Jain, Pankaj Kukkal:
Data-driven CAD or Algorithm-Driven CAD: Competitors or Collaborators? MLCAD 2020: 69
2010 – 2019
- 2018
- [j18]Justin M. Wozniak, Rajeev Jain, Prasanna Balaprakash, Jonathan Ozik, Nicholson T. Collier, John Bauer, Fangfang Xia, Thomas S. Brettin, Rick Stevens, Jamaludin Mohd-Yusof, Cristina Garcia-Cardona, Brian Van Essen, Matthew Baughman:
CANDLE/Supervisor: a workflow framework for machine learning applied to cancer research. BMC Bioinform. 19-S(18): 59-69 (2018) - [c24]Shankar Sadasivam, Zhuo Chen, Jinwon Lee, Rajeev Jain:
Efficient reinforcement learning for automating human decision-making in SoC design. DAC 2018: 37:1-37:6 - 2017
- [j17]H. C. Yadav, Rajeev Jain, Amit Raj Singh, P. K. Mishra:
Kano integrated robust design approach for aesthetical product design: a case study of a car profile. J. Intell. Manuf. 28(7): 1709-1727 (2017) - 2014
- [j16]Shwetank Avikal, Rajeev Jain, P. K. Mishra:
A Kano model, AHP and M-TOPSIS method-based technique for disassembly line balancing under fuzzy environment. Appl. Soft Comput. 25: 519-529 (2014) - [j15]Rajeev Jain, Amit Raj Singh, H. C. Yadav, P. K. Mishra:
Using data mining synergies for evaluating criteria at pre-qualification stage of supplier selection. J. Intell. Manuf. 25(1): 165-175 (2014) - 2013
- [j14]Shwetank Avikal, Rajeev Jain, P. K. Mishra, H. C. Yadav:
A heuristic approach for U-shaped assembly line balancing to improve labor productivity. Comput. Ind. Eng. 64(4): 895-901 (2013) - [c23]Rajeev Jain, Timothy J. Tautges:
PostBL: Post-mesh Boundary Layer Mesh Generation Tool. IMR 2013: 331-348 - 2012
- [j13]Timothy J. Tautges, Rajeev Jain:
Creating geometry and mesh models for nuclear reactor core geometries using a lattice hierarchy-based approach. Eng. Comput. 28(4): 319-329 (2012) - [c22]Shwetank Avikal, Rajeev Jain, Harish Yadav, P. K. Mishra:
A New Heuristic for Disassembly Line Balancing Problems with AND/OR Precedence Relations. SocProS 2012: 519-525 - 2010
- [c21]Timothy J. Tautges, Rajeev Jain:
Creating Geometry and Mesh Models for Nuclear Reactor Core Geometries Using a Lattice Hierarchy-Based Approach. IMR 2010: 351-365
2000 – 2009
- 2009
- [c20]Jihoon Park, Rajeev Jain, Danijela Cabric:
Spectrum Sensing Design Framework Based on Cross-Layer Optimization of Detection Efficiency. ICC 2009: 1-6
1990 – 1999
- 1999
- [j12]Charles Chien, Mani B. Srivastava, Rajeev Jain, Paul Lettieri, Vipin Aggarwal, Robert Sternowski:
Adaptive radio for multimedia wireless links. IEEE J. Sel. Areas Commun. 17(5): 793-813 (1999) - [c19]Kiran Bondalapati, Pedro C. Diniz, Phillip Duncan, John J. Granacki, Mary W. Hall, Rajeev Jain, Heidi E. Ziegler:
DEFACTO: A Design Environment for Adaptive Computing Technology. IPPS/SPDP Workshops 1999: 570-578 - 1998
- [j11]Stephen Molloy, Rajeev Jain:
A 110-K transistor 25-MPixels/s configurable image transform processor unit. IEEE J. Solid State Circuits 33(1): 86-97 (1998) - [c18]Rajeev Jain, Charles Chien, Etan G. Cohen, Leader Ho:
Simulation and Synthesis of VLSI Communication Systems. VLSI Design 1998: 336-341 - [c17]Rajeev Jain:
Panel: Challenges for Future Systems on a Chip. VLSI Design 1998: 578- - 1997
- [j10]H. O. Srivastava, Rajeev Jain:
On-line broadcast archives for interactive video. IEEE Trans. Broadcast. 43(3): 288-308 (1997) - 1996
- [j9]Charles Chien, Sean Nazareth, Paul Lettieri, Stephen Molloy, Brian Schoner, Walter A. Boring IV, Joey Chen, Christopher Deng, William H. Mangione-Smith, Rajeev Jain:
An integrated testbed for wireless multimedia computing. J. VLSI Signal Process. 13(2-3): 105-124 (1996) - [c16]William H. Mangione-Smith, Phil Seong Ghang, Sean Nazareth, Paul Lettieri, Walt Boring, Rajeev Jain:
A low power architecture for wireless multimedia systems: lessons learned from building a power hog. ISLPED 1996: 23-28 - [c15]Robert W. Brodersen, Rajeev Jain:
VLSI in Mobile Communication. VLSI Design 1996: 11-13 - 1995
- [j8]Phillip Duncan, Ken Kindsfater, Lynette Liu, Rajeev Jain:
Strategies for design automation of high speed digital filters. J. VLSI Signal Process. 9(1-2): 105-119 (1995) - [c14]Brian Schoner, John D. Villasenor, Steve Molloy, Rajeev Jain:
Techniques for FPGA Implementation of Video Compression Systems. FPGA 1995: 154-159 - 1994
- [j7]Charles Chien, Rajeev Jain, Etan G. Cohen, Henry Samueli:
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS. IEEE J. Solid State Circuits 29(12): 1614-1623 (1994) - [c13]Steve Molloy, Brian Schoner, Avanindra Madisetti, Rajeev Jain, Roy Matic:
An Algorithm-Driven Processor Design for Video Compression. ICIP (3) 1994: 611-615 - 1993
- [j6]Bong-Young Chung, Charles Chien, Henry Samueli, Rajeev Jain:
Performance Analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture. IEEE J. Sel. Areas Commun. 11(7): 1096-1107 (1993) - [c12]K. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli:
An Integrated Technology CAD System for Process and Device Designers. VLSI Design 1993: 287-292 - 1992
- [j5]Rajeev Jain, Avanindra Madisetti, Richard L. Baker:
An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller. IEEE Trans. Circuits Syst. Video Technol. 2(2): 147-158 (1992) - [j4]Linda Kwai-Lin Lau, Rajeev Jain, Henry Samueli, Henry T. Nicholas III, Etan G. Cohen:
DDFSGEN. J. VLSI Signal Process. 4(2-3): 213-226 (1992) - [c11]Avanindra Madisetti, Rajeev Jain, Richard L. Baker:
Real Time Implementation of Pruned Tree Search Vector Quantization. Data Compression Conference 1992: 152-161 - [c10]Soei-Shin Hang, Rajeev Jain:
Decimation filter compiler for oversampling A/D applications. ICASSP 1992: 537-540 - [c9]Philip Duncan, Shobana Swamy, Steve Sprouse, Daniel Potasz, Rajeev Jain, Neal M. Gafter, William Cammack, Yiwan Wong, Wanda Gass:
Hi-PASS: a computer-aided synthesis system for maximally parallel digital signal processing ASICs. ICASSP 1992: 605-608 - [c8]Avanindra Madisetti, Rajeev Jain, Richard L. Baker, Raffi Dianysian:
Architectures and integrated circuits for real time vector quantization of images. ICASSP 1992: 677-680 - 1991
- [j3]C. Bernard Shung, Rajeev Jain, Ken Rimey, Edward Wang, Mani B. Srivastava, Brian C. Richards, Erik Lettang, Syed Khalid Azim, Lars E. Thon, Paul N. Hilfinger, Jan M. Rabaey, Robert W. Brodersen:
An integrated CAD system for algorithm-specific IC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 447-463 (1991) - [j2]Rajeev Jain, Paul T. Yang, Toshiaki Yoshino:
FIRGEN: a computer-aided design system for high performance FIR filter integrated circuits. IEEE Trans. Signal Process. 39(7): 1655-1668 (1991) - [c7]Lynette Liu, Toshiaki Yoshino, Steven Sprouse, Rajeev Jain:
Computer-aided design of high-speed lattice wave digital filter integrated circuits. ICASSP 1991: 1229-1232 - 1990
- [c6]Paul T. Yang, Rajeev Jain, Toshiaki Yoshino, Wanda Gass, Ashwin Shah:
A functional silicon compiler for high speed FIR digital filters. ICASSP 1990: 1329-1332
1980 – 1989
- 1989
- [c5]Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild:
FDT-a design tool for switched capacitor filters. ICCAD 1989: 446-449 - 1988
- [j1]Francky Catthoor, Jan M. Rabaey, Gert Goossens, Jef L. van Meerbergen, Rajeev Jain, Hugo J. De Man, Joos Vandewalle:
Architectural strategies for an application-specific synchronous multiprocessor environment. IEEE Trans. Acoust. Speech Signal Process. 36(2): 265-284 (1988) - [c4]Francky Catthoor, Lawrence O'Gorman, Rajeev Jain:
An ASIC architecture for contour line filtering. ICASSP 1988: 1056-1059 - 1986
- [c3]Luc de Vos, Rajeev Jain, Hugo De Man, Walter Ulbrich:
A fast adder-based multiplication unit for customised digital signal processors. ICASSP 1986: 2163-2166 - 1985
- [c2]Rajeev Jain, Gert Goossens, Luc J. M. Claesen, Joos Vandewalle, Hugo De Man, L. Gazsi, Alfred Fettweis:
CAD Tools for the optimized design of custom VLSI wave digital filters. ICASSP 1985: 1465-1468 - 1984
- [c1]Rajeev Jain, Joos Vandewalle, Hugo De Man:
Efficient CAD tools for the coefficient optimisation of arbitrary integrated digital filters. ICASSP 1984: 602-605
Coauthor Index
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