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2020 – today
- 2024
[j7]Dongping Zhen
, Zerui Xu, Jiajie Yan, Yuan Tu, Changming Ding, Chi Zhang, She Chen, Lei Shan, Xiaohong Wang, Sixing Xu:
A Triboelectric Energy Harvesting IC With High-Voltage Synchronous Electric Charge Extraction Strategy and Superior Systematic Efficiency. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5349-5361 (2024)- 2020
- [j6]Lin Liang, Lei Shan, Fei Liu, Maolin Li, Ben Niu, Guanghua Xu:
Impulse Feature Extraction of Bearing Faults Based on Convolutive Nonnegative Matrix Factorization. IEEE Access 8: 88617-88632 (2020)
2010 – 2019
- 2017
- [c5]Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang:
Heterogeneous acceleration for CNN training with many integrated core. ICSPCC 2017: 1-6 - [c4]Naiyang Guan, Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang:
Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks. ISPA/IUCC 2017: 852-859 - 2016
- [c3]Lei Shan, Minxuan Zhang, Lin Deng, Guohui Gong:
A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network. NCCET 2016: 102-111 - [c2]Lei Shan, He Wang, Weixia Xu, Canqun Yang, Minxuan Zhang:
Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture. NCCET 2016: 168-176 - 2015
- [j5]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - 2014
- [j4]Wei Wei, Quan Xu, L. Wang, X. H. Hei, P. Shen, W. Shi, Lei Shan:
GI/Geom/1 queue based on communication model for mesh networks. Int. J. Commun. Syst. 27(11): 3013-3029 (2014) - [c1]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC 2014: 1-4
2000 – 2009
- 2006
- [j3]John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41(12): 2885-2900 (2006) - 2003
- [j2]Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer:
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47(2-3): 259-282 (2003) - 2002
- [j1]Mounir Meghelli, Alexander V. Rylyakov, Lei Shan:
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems. IEEE J. Solid State Circuits 37(12): 1790-1794 (2002)
Coauthor Index
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