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dblp: Mohamed Dessouky https://dblp.org/pid/43/944.html dblp person page RSS feed Mon, 07 Oct 2024 21:21:47 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Mohamed Dessoukyhttps://dblp.org/pid/43/944.html14451 A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs.https://doi.org/10.1109/ACCESS.2023.3265726, , :
A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs. IEEE Access 11: 36073-36081 ()]]>https://dblp.org/rec/journals/access/HabibDN23Sun, 01 Jan 2023 00:00:00 +0100 Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator.https://doi.org/10.1109/ACCESS.2023.3299227, , :
Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator. IEEE Access 11: 79721-79738 ()]]>https://dblp.org/rec/journals/access/MauriceDS23Sun, 01 Jan 2023 00:00:00 +0100 CLRGAN: Compressed Learning and Reconstruction Using GAN for Alzheimer's Disease.https://doi.org/10.1109/NILES59815.2023.10296647, , :
CLRGAN: Compressed Learning and Reconstruction Using GAN for Alzheimer's Disease. NILES : 327-332]]>https://dblp.org/rec/conf/niles/NaderDA23Sun, 01 Jan 2023 00:00:00 +0100 Design and Implementation of an Improved Variable Step-Size NLMS-Based Algorithm for Acoustic Noise Cancellation.https://doi.org/10.1007/s00034-021-01796-5, , :
Design and Implementation of an Improved Variable Step-Size NLMS-Based Algorithm for Acoustic Noise Cancellation. Circuits Syst. Signal Process. 41(1): 551-578 ()]]>https://dblp.org/rec/journals/cssp/SalahDA22Sat, 01 Jan 2022 00:00:00 +0100 Direct Digital Frequency Synthesizer Modeling with a Re-configurable DAC Evaluation for Electrochemical Impedance Spectroscopy.https://doi.org/10.1109/SENSORS52175.2022.9967147, , , :
Direct Digital Frequency Synthesizer Modeling with a Re-configurable DAC Evaluation for Electrochemical Impedance Spectroscopy. IEEE SENSORS : 1-4]]>https://dblp.org/rec/conf/ieeesensors/FaroukNMD22Sat, 01 Jan 2022 00:00:00 +0100 Common mode control loop for current mode logic-based circuits in FD-SOI technology.https://doi.org/10.1109/ISCAS48785.2022.9937899, , :
Common mode control loop for current mode logic-based circuits in FD-SOI technology. ISCAS : 1132-1133]]>https://dblp.org/rec/conf/iscas/SaifDA22Sat, 01 Jan 2022 00:00:00 +0100 Systematic Design For Multistage Feed-forward Op-amp For High-Speed Continuous-Time ∑Δ ADCs.https://doi.org/10.1109/ISCAS48785.2022.9937213, , , , :
Systematic Design For Multistage Feed-forward Op-amp For High-Speed Continuous-Time ∑Δ ADCs. ISCAS : 3219-3223]]>https://dblp.org/rec/conf/iscas/SaifSVDA22Sat, 01 Jan 2022 00:00:00 +0100 A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector.https://doi.org/10.1109/SOCC56010.2022.9908092, :
A General Algorithm for Loop-gain and TDC-resolution Optimization in an ADPLL with a 2-bit TDC Phase detector. SOCC : 1-6]]>https://dblp.org/rec/conf/socc/HabibD22Sat, 01 Jan 2022 00:00:00 +0100 A Novel Flow for Reducing Dynamic Power and Conditional Performance Improvement.https://doi.org/10.1109/TCSI.2021.3059347, , , :
A Novel Flow for Reducing Dynamic Power and Conditional Performance Improvement. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2003-2016 ()]]>https://dblp.org/rec/journals/tcasI/MostafaEDZ21Fri, 01 Jan 2021 00:00:00 +0100 A 6.4 GHz Continuous-Time ΣΔ ADC Using Body-Biased Feedforward Op-Amps in 28nm-FDSOI.https://doi.org/10.1109/MWSCAS47672.2021.9531739, , :
A 6.4 GHz Continuous-Time ΣΔ ADC Using Body-Biased Feedforward Op-Amps in 28nm-FDSOI. MWSCAS : 301-304]]>https://dblp.org/rec/conf/mwscas/SaifDA21Fri, 01 Jan 2021 00:00:00 +0100 Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison.https://doi.org/10.1109/MWSCAS47672.2021.9531753, , , :
Digital ASIC Implementation of RISC-V: OpenLane and Commercial Approaches in Comparison. MWSCAS : 498-502]]>https://dblp.org/rec/conf/mwscas/HeshamSED21Fri, 01 Jan 2021 00:00:00 +0100 A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower.https://doi.org/10.1016/j.mejo.2020.104817, , :
A fabrication of a low-power low-noise neural recording amplifier based on flipped voltage follower. Microelectron. J. 101: 104817 ()]]>https://dblp.org/rec/journals/mj/FaroukDE20Wed, 01 Jan 2020 00:00:00 +0100 Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA.https://doi.org/10.1109/ICSET51301.2020.9265388, , :
Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA. ICSET : 179-184]]>https://dblp.org/rec/conf/icsengt/AhmedGD20Wed, 01 Jan 2020 00:00:00 +0100 Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits.https://doi.org/10.1109/ISQED48828.2020.9137046, , :
Electrostatic Discharge Physical Verification of 2.5D/3D Integrated Circuits. ISQED : 383-388]]>https://dblp.org/rec/conf/isqed/MedhatDK20Wed, 01 Jan 2020 00:00:00 +0100 Fragile HFSM Watermarking Hardware IP Authentication CAD Tool.https://doi.org/10.1109/MOCAST49295.2020.9200266, , :
Fragile HFSM Watermarking Hardware IP Authentication CAD Tool. MOCAST : 1-6]]>https://dblp.org/rec/conf/mocast/ShukryAD20Wed, 01 Jan 2020 00:00:00 +0100 IPXACT-Based RTL Generation Tool.https://doi.org/10.1109/NILES50944.2020.9257966, , , , , , :
IPXACT-Based RTL Generation Tool. NILES : 71-74]]>https://dblp.org/rec/conf/niles/El-ShiekhEAGDSM20Wed, 01 Jan 2020 00:00:00 +0100 Systolic-based pyramidal neuron accelerator blocks for convolutional neural network.https://doi.org/10.1016/j.mejo.2019.04.017, , :
Systolic-based pyramidal neuron accelerator blocks for convolutional neural network. Microelectron. J. 89: 16-22 ()]]>https://dblp.org/rec/journals/mj/AhmedGD19Tue, 01 Jan 2019 00:00:00 +0100 Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses.https://doi.org/10.1109/ICM48031.2019.9021657, , , , , , :
Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses. ICM : 195-198]]>https://dblp.org/rec/conf/icm2/HussienMSMSDM19Tue, 01 Jan 2019 00:00:00 +0100 Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators.https://doi.org/10.1109/ISCAS.2019.8702717, , , , :
Gm-Free Assisted Opamp Technique for Continuous Time Delta-Sigma Modulators. ISCAS : 1-4]]>https://dblp.org/rec/conf/iscas/ElShaterLVDM19Tue, 01 Jan 2019 00:00:00 +0100 A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate.https://doi.org/10.1109/PACRIM47961.2019.8985099, , , :
A Dynamic Power Reduction Methodology based on Reducing Output Transition Rate. PACRIM : 1-6]]>https://dblp.org/rec/conf/pacrim/MostafaZED19Tue, 01 Jan 2019 00:00:00 +0100 Analog Layout Placement Based on Unit Elements and Routing Channel Estimation.https://doi.org/10.1109/SMACD.2019.8795235, , , :
Analog Layout Placement Based on Unit Elements and Routing Channel Estimation. SMACD : 29-32]]>https://dblp.org/rec/conf/smacd/MohamedDNH19Tue, 01 Jan 2019 00:00:00 +0100 PLL Real Number Modeling in SystemVerilog.https://doi.org/10.1109/SMACD.2019.8795233, , :
PLL Real Number Modeling in SystemVerilog. SMACD : 257-260]]>https://dblp.org/rec/conf/smacd/LouisDS19Tue, 01 Jan 2019 00:00:00 +0100 Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology.https://doi.org/10.1016/j.mejo.2018.02.002, , :
Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology. Microelectron. J. 75: 87-96 ()]]>https://dblp.org/rec/journals/mj/SabryOD18Mon, 01 Jan 2018 00:00:00 +0100 Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA.https://doi.org/10.1109/AHS.2018.8541491, , :
Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. AHS : 104-111]]>https://dblp.org/rec/conf/ahs/AhmedGD18Mon, 01 Jan 2018 00:00:00 +0100 Affirming Hardware Design Authenticity Using Fragile IP Watermarking.https://doi.org/10.1109/COMAPP.2018.8460369, , :
Affirming Hardware Design Authenticity Using Fragile IP Watermarking. ICCA : 341-347]]>https://dblp.org/rec/conf/icca3/ShukryAD18Mon, 01 Jan 2018 00:00:00 +0100 High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network.https://doi.org/10.1007/978-3-030-01054-6_47, , :
High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network. IntelliSys (1) : 655-663]]>https://dblp.org/rec/conf/intellisys/AhmedGD18Mon, 01 Jan 2018 00:00:00 +0100 Mismatch-Aware Placement of Device Arrays Using Genetic Optimization.https://doi.org/10.1109/SMACD.2018.8434886, , , :
Mismatch-Aware Placement of Device Arrays Using Genetic Optimization. SMACD : 177-180]]>https://dblp.org/rec/conf/smacd/NashaatMDS18Mon, 01 Jan 2018 00:00:00 +0100 Forty years of Computers & Industrial Engineering: A bibliometric analysis.https://doi.org/10.1016/j.cie.2017.08.033, , , , :
Forty years of Computers & Industrial Engineering: A bibliometric analysis. Comput. Ind. Eng. 113: 614-629 ()]]>https://dblp.org/rec/journals/candie/CancinoMCDD17Sun, 01 Jan 2017 00:00:00 +0100 Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits.https://doi.org/10.23919/DATE.2017.7927192, , :
Power pre-characterized meshing algorithm for finite element thermal analysis of integrated circuits. DATE : 1293-1296]]>https://dblp.org/rec/conf/date/AbdelkaderED17Sun, 01 Jan 2017 00:00:00 +0100 Monte Carlo general sample classification for rare circuit events using Random Forest.https://doi.org/10.1109/SMACD.2017.7981599, :
Monte Carlo general sample classification for rare circuit events using Random Forest. SMACD : 1-4]]>https://dblp.org/rec/conf/smacd/El-AdawiD17Sun, 01 Jan 2017 00:00:00 +0100 Analog layout placement retargeting using Satisfiability Modulo Theories.https://doi.org/10.1109/SMACD.2017.7981569, , :
Analog layout placement retargeting using Satisfiability Modulo Theories. SMACD : 1-4]]>https://dblp.org/rec/conf/smacd/MohamedDS17Sun, 01 Jan 2017 00:00:00 +0100 A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories.https://doi.org/10.1142/S021812661650047X, , , , :
A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories. J. Circuits Syst. Comput. 25(5): 1650047:1-1650047:31 ()]]>https://dblp.org/rec/journals/jcsc/SaifDEAN16Fri, 01 Jan 2016 00:00:00 +0100 Pareto front analog layout placement using Satisfiability Modulo Theories.https://ieeexplore.ieee.org/document/7459529/, , , , :
Pareto front analog layout placement using Satisfiability Modulo Theories. DATE : 1411-1416]]>https://dblp.org/rec/conf/date/SaifDEAN16Fri, 01 Jan 2016 00:00:00 +0100 12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications.https://doi.org/10.1109/ICECS.2016.7841142, , , :
12-Gb/s low-power voltage-mode driver for multi-standard serial-link applications. ICECS : 101-104]]>https://dblp.org/rec/conf/icecsys/MegahedRID16Fri, 01 Jan 2016 00:00:00 +0100 A simple model for on-chip microstrip transmission lines in millimeter wave circuits.https://doi.org/10.1109/ICM.2016.7847924, , , , , :
A simple model for on-chip microstrip transmission lines in millimeter wave circuits. ICM : 121-124]]>https://dblp.org/rec/conf/icm2/ShafieEDSHH16Fri, 01 Jan 2016 00:00:00 +0100 Optimally matched current mirror layout pattern generation using genetic optimization.https://doi.org/10.1109/ICM.2016.7847930, , :
Optimally matched current mirror layout pattern generation using genetic optimization. ICM : 145-148]]>https://dblp.org/rec/conf/icm2/DinDS16Fri, 01 Jan 2016 00:00:00 +0100 Regression modeling for subset selection in rare-event statistical circuit simulation.https://doi.org/10.1109/IDT.2016.7843041, :
Regression modeling for subset selection in rare-event statistical circuit simulation. IDT : 205-209]]>https://dblp.org/rec/conf/idt/El-AdawiD16Fri, 01 Jan 2016 00:00:00 +0100 Stress-aware analog layout devices pattern generation.https://doi.org/10.1109/IDT.2016.7843046, :
Stress-aware analog layout devices pattern generation. IDT : 233-238]]>https://dblp.org/rec/conf/idt/El-KenawyD16Fri, 01 Jan 2016 00:00:00 +0100 Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis.https://doi.org/10.1109/ISCAS.2016.7538951, , , :
Accuracy-improved coupling capacitance model for through-silicon via (TSV) arrays using dimensional analysis. ISCAS : 1930-1933]]>https://dblp.org/rec/conf/iscas/RamadanYDI16Fri, 01 Jan 2016 00:00:00 +0100 Transaction Level Power Modeling (TLPM) Methodology.https://doi.org/10.1109/MTV.2016.21, , :
Transaction Level Power Modeling (TLPM) Methodology. MTV : 61-64]]>https://dblp.org/rec/conf/mtv/DarwishED16Fri, 01 Jan 2016 00:00:00 +0100 Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting.https://doi.org/10.1109/MWSCAS.2016.7870073, , , :
Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting. MWSCAS : 1-4]]>https://dblp.org/rec/conf/mwscas/EmadMGD16Fri, 01 Jan 2016 00:00:00 +0100 Optimization of the output power of a frequency-up conversion piezoelectric energy harvester.https://doi.org/10.1109/MWSCAS.2016.7870050, , , :
Optimization of the output power of a frequency-up conversion piezoelectric energy harvester. MWSCAS : 1-4]]>https://dblp.org/rec/conf/mwscas/ShadoufaMGD16Fri, 01 Jan 2016 00:00:00 +0100 Analog layout placement exploiting sub-block shape functions.https://doi.org/10.1109/SMACD.2016.7520735, , :
Analog layout placement exploiting sub-block shape functions. SMACD : 1-4]]>https://dblp.org/rec/conf/smacd/El-KenawyMD16Fri, 01 Jan 2016 00:00:00 +0100 Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories.https://doi.org/10.1109/DTIS.2015.7127355, , , , :
Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories. DTIS : 1-6]]>https://dblp.org/rec/conf/dtis/SaifDAEN15Thu, 01 Jan 2015 00:00:00 +0100 A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter.https://doi.org/10.1109/ICECS.2015.7440315, , , :
A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter. ICECS : 328-331]]>https://dblp.org/rec/conf/icecsys/HamzaIED15Thu, 01 Jan 2015 00:00:00 +0100 Optimal design of 6T SRAM bitcells for ultra low-voltage operation.https://doi.org/10.1109/ICECS.2015.7440346, , :
Optimal design of 6T SRAM bitcells for ultra low-voltage operation. ICECS : 454-457]]>https://dblp.org/rec/conf/icecsys/GhonemFD15Thu, 01 Jan 2015 00:00:00 +0100 An 8kb SRAM macro in 65nm for ultra-low voltage applications operating from 1.2V to 0.5V.https://doi.org/10.1109/ICECS.2015.7440347, , :
An 8kb SRAM macro in 65nm for ultra-low voltage applications operating from 1.2V to 0.5V. ICECS : 458-461]]>https://dblp.org/rec/conf/icecsys/FaridGD15Thu, 01 Jan 2015 00:00:00 +0100 Coupling capacitance extraction in through-silicon via (TSV) arrays.https://doi.org/10.1109/ICECS.2015.7440350, , , :
Coupling capacitance extraction in through-silicon via (TSV) arrays. ICECS : 470-473]]>https://dblp.org/rec/conf/icecsys/RamadanYDI15Thu, 01 Jan 2015 00:00:00 +0100 Procedural analog design automation using building block optimization.https://doi.org/10.1109/ICECS.2015.7440351, :
Procedural analog design automation using building block optimization. ICECS : 474-477]]>https://dblp.org/rec/conf/icecsys/El-SisiD15Thu, 01 Jan 2015 00:00:00 +0100 Incremental layout-aware analog design methodology.https://doi.org/10.1109/ICECS.2015.7440354, :
Incremental layout-aware analog design methodology. ICECS : 486-489]]>https://dblp.org/rec/conf/icecsys/ElshawyD15Thu, 01 Jan 2015 00:00:00 +0100 Structure optimization for efficient AlN piezoelectric energy harvesters.https://doi.org/10.1109/ICECS.2015.7440370, , , , :
Structure optimization for efficient AlN piezoelectric energy harvesters. ICECS : 527-530]]>https://dblp.org/rec/conf/icecsys/ShadoufaEGMD15Thu, 01 Jan 2015 00:00:00 +0100 A 1V low-power low-noise biopotential amplifier based on flipped voltage follower.https://doi.org/10.1109/ICECS.2015.7440373, , :
A 1V low-power low-noise biopotential amplifier based on flipped voltage follower. ICECS : 539-542]]>https://dblp.org/rec/conf/icecsys/FaroukED15Thu, 01 Jan 2015 00:00:00 +0100 Parameterized test patterns methodology for layout design rule checking verification.https://doi.org/10.1109/ICECS.2015.7440385, , , :
Parameterized test patterns methodology for layout design rule checking verification. ICECS : 588-591]]>https://dblp.org/rec/conf/icecsys/TantawyGDA15Thu, 01 Jan 2015 00:00:00 +0100 A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation.https://doi.org/10.1109/IDT.2015.7396734, , :
A low-temperature-coefficient curvature-compensated bandgap reference with mismatch attenuation. IDT : 44-48]]>https://dblp.org/rec/conf/idt/EladwyID15Thu, 01 Jan 2015 00:00:00 +0100 A design flow to quantify and limit multiple patterning effects.https://doi.org/10.1109/MWSCAS.2015.7282106, :
A design flow to quantify and limit multiple patterning effects. MWSCAS : 1-4]]>https://dblp.org/rec/conf/mwscas/HarbD15Thu, 01 Jan 2015 00:00:00 +0100 An 8Gbps discrete time linear equalizer in 40nm CMOS technology.https://doi.org/10.1109/MWSCAS.2015.7282098, , :
An 8Gbps discrete time linear equalizer in 40nm CMOS technology. MWSCAS : 1-4]]>https://dblp.org/rec/conf/mwscas/IsmailID15Thu, 01 Jan 2015 00:00:00 +0100 A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS.https://doi.org/10.1109/NEWCAS.2015.7182045, , , :
A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS. NEWCAS : 1-4]]>https://dblp.org/rec/conf/newcas/HamzaIED15Thu, 01 Jan 2015 00:00:00 +0100 SystemVerilog assertion debugging: A visualization and pattern matching model.https://doi.org/10.1109/PACRIM.2015.7334867, , , :
SystemVerilog assertion debugging: A visualization and pattern matching model. PACRIM : 385-390]]>https://dblp.org/rec/conf/pacrim/MostafaSED15Thu, 01 Jan 2015 00:00:00 +0100 Exploiting satisfiability modulo theories for analog layout automation.https://doi.org/10.1109/IDT.2014.7038590, , , , , :
Exploiting satisfiability modulo theories for analog layout automation. IDT : 1-6]]>https://dblp.org/rec/conf/idt/SaifDNAEA14Wed, 01 Jan 2014 00:00:00 +0100 Multi-device layout templates for nanometer analog design.https://doi.org/10.1109/IDT.2014.7038592, , , , :
Multi-device layout templates for nanometer analog design. IDT : 83-88]]>https://dblp.org/rec/conf/idt/ElshawyDSMP14Wed, 01 Jan 2014 00:00:00 +0100 The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs.https://doi.org/10.1145/2685342.2685348, , :
The Connection-Then-Credit Flow Control Protocol for Networks-On-Chips: Implementation Trade-offs. NoCArc@MICRO : 25-30]]>https://dblp.org/rec/conf/micro/SallamED14Wed, 01 Jan 2014 00:00:00 +0100 System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation.https://doi.org/10.1109/MTV.2014.23, , , :
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. MTV : 55-60]]>https://dblp.org/rec/conf/mtv/MostafaSED14Wed, 01 Jan 2014 00:00:00 +0100 A 8 Gbps 0.67mW 1 tap current integrating DFE in 40nm CMOS.https://doi.org/10.1109/MWSCAS.2014.6908357, , :
A 8 Gbps 0.67mW 1 tap current integrating DFE in 40nm CMOS. MWSCAS : 81-84]]>https://dblp.org/rec/conf/mwscas/IsmailID14Wed, 01 Jan 2014 00:00:00 +0100 Don't cares based dynamic test vector compaction in SAT-ATPG.https://doi.org/10.1109/MWSCAS.2014.6908390, , , :
Don't cares based dynamic test vector compaction in SAT-ATPG. MWSCAS : 213-217]]>https://dblp.org/rec/conf/mwscas/HabibSDS14Wed, 01 Jan 2014 00:00:00 +0100 Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow.https://doi.org/10.1109/TVLSI.2012.2201759, , , , , , , :
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 807-820 ()]]>https://dblp.org/rec/journals/tvlsi/EissaSAHEDNA13Tue, 01 Jan 2013 00:00:00 +0100 A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization.https://doi.org/10.1109/ICECS.2013.6815378, , :
A programmable 8-bit, 10MHz BW, 6.8mW, 200MSample/sec, 70dB SNDR VCO-based ADC using SC feedback for VCO linearization. ICECS : 157-160]]>https://dblp.org/rec/conf/icecsys/El-HalwagyDE13Tue, 01 Jan 2013 00:00:00 +0100 Analysis and design of analog-based voltage controlled oscillator linearization technique.https://doi.org/10.1109/IDT.2013.6727106, , :
Analysis and design of analog-based voltage controlled oscillator linearization technique. IDT : 1-6]]>https://dblp.org/rec/conf/idt/El-HalwagyDE13Tue, 01 Jan 2013 00:00:00 +0100 Dr. Mohamed Sadek Eid 1938-2012.https://doi.org/10.1016/j.cie.2012.09.007:
Dr. Mohamed Sadek Eid 1938-2012. Comput. Ind. Eng. 63(4): 1243 ()]]>https://dblp.org/rec/journals/candie/Dessouky12Sun, 01 Jan 2012 00:00:00 +0100 Web-based analog design using tradeoff charts.https://doi.org/10.1109/ICECS.2012.6463712, , , , :
Web-based analog design using tradeoff charts. ICECS : 13-16]]>https://dblp.org/rec/conf/icecsys/HamzaPADK12Sun, 01 Jan 2012 00:00:00 +0100 Channel mismatch background calibration for pipelined time interleaved ADCs.https://doi.org/10.1109/ICECS.2012.6463673, :
Channel mismatch background calibration for pipelined time interleaved ADCs. ICECS : 609-612]]>https://dblp.org/rec/conf/icecsys/MrassyD12Sun, 01 Jan 2012 00:00:00 +0100 Layout stress and proximity aware analog design methodology.https://doi.org/10.1109/ICECS.2012.6463667, , , , , , :
Layout stress and proximity aware analog design methodology. ICECS : 633-636]]>https://dblp.org/rec/conf/icecsys/ZeinTBDERT12Sun, 01 Jan 2012 00:00:00 +0100 Schematic-driven physical verification: Fully automated solution for analog IC design.https://doi.org/10.1109/SOCC.2012.6398358, , , , , , :
Schematic-driven physical verification: Fully automated solution for analog IC design. SoCC : 260-264]]>https://dblp.org/rec/conf/socc/ArafaWFFMAD12Sun, 01 Jan 2012 00:00:00 +0100 An electrical-aware parametric DFM solution for analog circuits.https://doi.org/10.1109/IDT.2011.6123104, , , , , , , :
An electrical-aware parametric DFM solution for analog circuits. IDT : 68-73]]>https://dblp.org/rec/conf/idt/SalemAHEEDNA11Sat, 01 Jan 2011 00:00:00 +0100 Design of tunable continuous-time quadrature bandpass delta-sigma modulators.https://doi.org/10.1109/IDT.2011.6123110, , :
Design of tunable continuous-time quadrature bandpass delta-sigma modulators. IDT : 99-103]]>https://dblp.org/rec/conf/idt/SakrDZ11Sat, 01 Jan 2011 00:00:00 +0100 A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow.https://doi.org/10.1109/SOCC.2011.6085082, , , , , , , :
A parametric DFM solution for analog circuits: Electrical driven hot spot detection, analysis and correction flow. SoCC : 231-236]]>https://dblp.org/rec/conf/socc/SalemAHEEDNA11Sat, 01 Jan 2011 00:00:00 +0100 A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs.https://doi.org/10.1109/IDT.2010.5724398, , , , :
A DFM tool for analyzing lithography and stress effects on standard cells and critical path performance in 45nm digital designs. IDT : 13-17]]>https://dblp.org/rec/conf/idt/SalemEEDA10Fri, 01 Jan 2010 00:00:00 +0100 Foreground digital calibration of non-linear errors in pipelined A/D converters.https://doi.org/10.1109/ISCAS.2010.5537533, , , , :
Foreground digital calibration of non-linear errors in pipelined A/D converters. ISCAS : 569-572]]>https://dblp.org/rec/conf/iscas/AdelDLGH10Fri, 01 Jan 2010 00:00:00 +0100 13-bit 205 MS/s time-interleaved pipelined ADC with digital background calibration.https://doi.org/10.1109/ISCAS.2010.5537535, :
13-bit 205 MS/s time-interleaved pipelined ADC with digital background calibration. ISCAS : 1727-1730]]>https://dblp.org/rec/conf/iscas/MohsenD10Fri, 01 Jan 2010 00:00:00 +0100 Extended division range 2/3 chain frequency divider with dynamic control word.https://doi.org/10.1109/ISCAS.2010.5537604, , :
Extended division range 2/3 chain frequency divider with dynamic control word. ISCAS : 4141-4144]]>https://dblp.org/rec/conf/iscas/AshourDS10Fri, 01 Jan 2010 00:00:00 +0100 Design of a low-power ZigBee receiver front-end for wireless sensors.https://doi.org/10.1016/j.mejo.2009.03.002, , :
Design of a low-power ZigBee receiver front-end for wireless sensors. Microelectron. J. 40(11): 1561-1568 ()]]>https://dblp.org/rec/journals/mj/HafezDR09Thu, 01 Jan 2009 00:00:00 +0100 Analog design migration: An overview.https://doi.org/10.1109/ICECS.2009.5410841:
Analog design migration: An overview. ICECS : 992-995]]>https://dblp.org/rec/conf/icecsys/Dessouky09Thu, 01 Jan 2009 00:00:00 +0100 1-V, High Speed, Low Leakage CMOS CML Multiplexer.https://doi.org/10.1109/ISCAS.2009.5118472, , :
1-V, High Speed, Low Leakage CMOS CML Multiplexer. ISCAS : 3154-3157]]>https://dblp.org/rec/conf/iscas/AbdelkaderOD09Thu, 01 Jan 2009 00:00:00 +0100 A Case-Based Reasoning Approach for the Automatic Generation of VHDL-AMS Models.https://doi.org/10.1109/BMAS.2008.4751249, , , :
A Case-Based Reasoning Approach for the Automatic Generation of VHDL-AMS Models. BMAS : 100-105]]>https://dblp.org/rec/conf/bmas/Al-KashefZDE08Tue, 01 Jan 2008 00:00:00 +0100 Chameleon ART: a non-optimization based analog design migration framework.https://doi.org/10.1145/1146909.1147134, , , , , , , :
Chameleon ART: a non-optimization based analog design migration framework. DAC : 885-888]]>https://dblp.org/rec/conf/dac/HammoudaSDTNBAS06Sun, 01 Jan 2006 00:00:00 +0100 Forward.https://doi.org/10.1016/j.cie.2004.12.001, , :
Forward. Comput. Ind. Eng. 48(4): 679-680 ()]]>https://dblp.org/rec/journals/candie/PapadopoulosOD05Sat, 01 Jan 2005 00:00:00 +0100 Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays.https://doi.org/10.1109/ISQED.2005.54, , , , , :
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays. ISQED : 143-147]]>https://dblp.org/rec/conf/isqed/KhalilDBLCR05Sat, 01 Jan 2005 00:00:00 +0100 Analog IP migration using design knowledge extraction.https://doi.org/10.1109/CICC.2004.1358813, , , :
Analog IP migration using design knowledge extraction. CICC : 333-336]]>https://dblp.org/rec/conf/cicc/HammoudaDTB04Thu, 01 Jan 2004 00:00:00 +0100 A Fully Automated Approach for Analog Circuit Reuse.https://doi.org/10.1109/IWSOC.2004.1319886, , , :
A Fully Automated Approach for Analog Circuit Reuse. IWSOC : 237-240]]>https://dblp.org/rec/conf/iwsoc/HammoudaDTB04Thu, 01 Jan 2004 00:00:00 +0100 Synthesis of CMOS Analog Cells Using AMIGO.https://doi.org/10.1109/DATE.2003.1186712, , , , , , :
Synthesis of CMOS Analog Cells Using AMIGO. DATE : 20297-20302]]>https://dblp.org/rec/conf/date/IskanderDAMHSM03Wed, 01 Jan 2003 00:00:00 +0100 Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio.https://doi.org/10.1109/DATE.2002.998358, :
Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio. DATE : 576-580]]>https://dblp.org/rec/conf/date/DessoukyS02Tue, 01 Jan 2002 00:00:00 +0100 Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping.https://doi.org/10.1109/4.910473, :
Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping. IEEE J. Solid State Circuits 36(3): 349-355 ()]]>https://dblp.org/rec/journals/jssc/DessoukyK01Mon, 01 Jan 2001 00:00:00 +0100 Analog design for reuse - case study: very low-voltage sigma-delta modulator.https://doi.org/10.1109/DATE.2001.915049, , , :
Analog design for reuse - case study: very low-voltage sigma-delta modulator. DATE : 353-360]]>https://dblp.org/rec/conf/date/DessoukyKLG01Mon, 01 Jan 2001 00:00:00 +0100 Switch sizing for very low-voltage switched-capacitor circuits.https://doi.org/10.1109/ICECS.2001.957511, , :
Switch sizing for very low-voltage switched-capacitor circuits. ICECS : 1549-1552]]>https://dblp.org/rec/conf/icecsys/DessoukyLK01Mon, 01 Jan 2001 00:00:00 +0100 A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping.https://doi.org/10.1109/CICC.2000.852608, :
A 1 V 1 mW digital-audio ΔΣ modulator with 88 dB dynamic range using local switch bootstrapping. CICC : 13-16]]>https://dblp.org/rec/conf/cicc/DessoukyK00Sat, 01 Jan 2000 00:00:00 +0100 Layout-Oriented Synthesis of High Performance Analog Circuits.https://doi.org/10.1109/DATE.2000.840015, , :
Layout-Oriented Synthesis of High Performance Analog Circuits. DATE : 53-57]]>https://dblp.org/rec/conf/date/DessoukyLP00Sat, 01 Jan 2000 00:00:00 +0100 Very low-voltage fully differential amplifier for switched-capacitor applications.https://doi.org/10.1109/ISCAS.2000.857466, :
Very low-voltage fully differential amplifier for switched-capacitor applications. ISCAS : 441-444]]>https://dblp.org/rec/conf/iscas/DessoukyK00Sat, 01 Jan 2000 00:00:00 +0100 A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits.https://doi.org/10.1109/ISQED.2000.838885, :
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits. ISQED : 291-298]]>https://dblp.org/rec/conf/isqed/DessoukyL00Sat, 01 Jan 2000 00:00:00 +0100 Optimized Statistical Analog Fault Simulation.https://doi.org/10.1109/ATS.1999.810755, , :
Optimized Statistical Analog Fault Simulation. Asian Test Symposium : 227-232]]>https://dblp.org/rec/conf/ats/KhouasDD99Fri, 01 Jan 1999 00:00:00 +0100 A third-order current-mode continuous-time ΣΔ modulator.https://doi.org/10.1109/ICECS.1999.814502, , , :
A third-order current-mode continuous-time ΣΔ modulator. ICECS : 1697-1700]]>https://dblp.org/rec/conf/icecsys/AboushadyDML99Fri, 01 Jan 1999 00:00:00 +0100 Rail-to-rail operation of very low voltage CMOS switched-capacitor circuits.https://doi.org/10.1109/ISCAS.1999.780639, :
Rail-to-rail operation of very low voltage CMOS switched-capacitor circuits. ISCAS (2) : 144-147]]>https://dblp.org/rec/conf/iscas/DessoukyK99Fri, 01 Jan 1999 00:00:00 +0100 A current-mode continuous-time Sigma-Delta modulator with delayed return-to-zero feedback.https://doi.org/10.1109/ISCAS.1999.780733, , , :
A current-mode continuous-time Sigma-Delta modulator with delayed return-to-zero feedback. ISCAS (2) : 360-363]]>https://dblp.org/rec/conf/iscas/AboushadyMDL99Fri, 01 Jan 1999 00:00:00 +0100