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2020 – today
- 2021
[c48]Sambit Kumar Shukla, Dipak Ghosal
, Matthew K. Farrens:
Understanding and Leveraging Cluster Heterogeneity for Efficient Execution of Cloud Services. CloudNet 2021: 56-64- [c47]Sambit Kumar Shukla, Matthew K. Farrens:
Leveraging Network Delay Variability to Improve QoE of Latency Critical Services. NAS 2021: 1-8 - 2020
- [j14]Goldwayne Smith Leh, Jian Wu, Sambit Shukla, Matthew K. Farrens, Dipak Ghosal:
Model-Driven Joint Optimization of Power and Latency Guarantee in Data center Applications. SN Comput. Sci. 1(1): 34:1-34:14 (2020) - [c46]Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
HCAPP: Scalable Power Control for Heterogeneous 2.5D Integrated Systems. ICPP 2020: 60:1-60:11
2010 – 2019
- 2019
- [c45]Sambit Shukla, Dipak Ghosal, Kesheng Wu, Alex Sim, Matthew K. Farrens:
Co-optimizing Latency and Energy for IoT services using HMP servers in Fog Clusters. FMEC 2019: 121-128 - [c44]Sambit Kumar Shukla, Dipak Ghosal, Matthew K. Farrens:
Tuning Network I/O Processing to Achieve Performance and Energy Objectives of Latency Critical Workloads. HPCC/SmartCity/DSS 2019: 1499-1508 - 2018
- [j13]Nathan Hanford, Vishal Ahuja, Matthew K. Farrens, Brian Tierney, Dipak Ghosal:
A Survey of End-System Optimizations for High-Speed Networks. ACM Comput. Surv. 51(3): 54:1-54:36 (2018) - [c43]Kramer Straube, Jason Lowe-Power, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Improving Provisioned Power Efficiency in HPC Systems with GPU-CAPP. HiPC 2018: 112-122 - [c42]Jason Lowe-Power, Venkatesh Akella, Matthew K. Farrens, Samuel T. King, Christopher J. Nitta:
A case for exposing extra-architectural state in the ISA: position paper. HASP@ISCA 2018: 8:1-8:6 - 2017
- [c41]David Fridovich-Keil, Nathan Hanford, Margaret P. Chapman, Claire J. Tomlin, Matthew K. Farrens, Dipak Ghosal:
A model predictive control approach to flow pacing for TCP. Allerton 2017: 988-994 - [c40]Kramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power Processing. ICCD 2017: 649-652 - 2016
- [j12]Nathan Hanford, Vishal Ahuja, Matthew K. Farrens, Dipak Ghosal, Mehmet Balman, Eric Pouyoul, Brian Tierney:
Improving network performance on multicore systems: Impact of core affinities on high throughput flows. Future Gener. Comput. Syst. 56: 277-283 (2016) - 2015
- [c39]Ross K. Gegan, Rennie Archibald, Matthew K. Farrens, Dipak Ghosal:
Performance Analysis of Real-Time Covert Timing Channel Detection Using a Parallel System. NSS 2015: 519-530 - 2014
- [j11]Kevin Macdonald, Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks. IEEE Trans. Computers 63(3): 650-663 (2014) - [j10]Paul Congdon, Prasant Mohapatra, Matthew K. Farrens, Venkatesh Akella:
Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches. IEEE/ACM Trans. Netw. 22(3): 1007-1020 (2014) - [c38]Nathan Hanford, Vishal Ahuja, Matthew K. Farrens, Dipak Ghosal, Mehmet Balman, Eric Pouyoul, Brian Tierney:
Impact of the end-system and affinities on the throughput of high-speed flows. ANCS 2014: 259-260 - [c37]Nathan Hanford, Vishal Ahuja, Matthew K. Farrens, Dipak Ghosal, Mehmet Balman, Eric Pouyoul, Brian Tierney:
Analysis of the effect of core affinity on high-throughput flows. NDM@SC 2014: 9-15 - 2013
- [b1]Christopher Nitta, Matthew K. Farrens:
Photonic Interconnects: A Computer Architect's Perspective. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2013, ISBN 9781627052115, pp. 1-111 - [c36]Nathan Hanford, Vishal Ahuja, Mehmet Balman, Matthew K. Farrens, Dipak Ghosal, Eric Pouyoul, Brian Tierney:
Characterizing the impact of end-system affinities on the end-to-end performance of high-speed flows. NDM@SC 2013: 1:1-1:10 - [e3]Matthew K. Farrens, Christos Kozyrakis:
The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013. ACM 2013, ISBN 978-1-4503-2638-4 [contents] - 2012
- [j9]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
DCOF - An Arbitration Free Directly Connected Optical Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 169-182 (2012) - [c35]Vishal Ahuja, Matthew K. Farrens, Dipak Ghosal:
Cache-aware affinitization on commodity multicores for high-speed network flows. ANCS 2012: 39-48 - [c34]Vishal Ahuja, Dipak Ghosal, Matthew K. Farrens:
Minimizing the Data Transfer Time Using Multicore End-System Aware Flow Bifurcation. CCGRID 2012: 595-602 - [c33]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing. IPDPS 2012: 1144-1155 - 2011
- [c32]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Addressing system-level trimming issues in on-chip nanophotonic networks. HPCA 2011: 122-131 - [c31]Vishal Ahuja, Amitabha Banerjee, Matthew K. Farrens, Dipak Ghosal, Giuseppe Serazzi:
Introspective end-system modeling to optimize the transfer time of rate based protocols. HPDC 2011: 61-72 - [c30]Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Resilient microring resonator based photonic networks. MICRO 2011: 95-104 - [c29]Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella:
Inferring packet dependencies to improve trace based simulation of on-chip networks. NOCS 2011: 153-160 - 2010
- [c28]Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Performance Evaluation of a Multicore System with Optically Connected Memory Modules. NOCS 2010: 215-222
2000 – 2009
- 2008
- [c27]Paul Congdon, Matthew K. Farrens, Prasant Mohapatra:
Packet prediction for speculative cut-through switching. ANCS 2008: 99-108 - [c26]Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella:
Design and evaluation of an optical CPU-DRAM interconnect. ICCD 2008: 492-497 - [c25]Christopher Nitta, Matthew K. Farrens:
Techniques for increasing effective data bandwidth. ICCD 2008: 514-519 - 2002
- [j8]Mark Oskin, Frederic T. Chong, Matthew K. Farrens:
Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation. J. Instr. Level Parallelism 4 (2002) - 2001
- [j7]Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens:
Improving Bandwidth Utilization using Eager Writeback. J. Instr. Level Parallelism 3 (2001) - 2000
- [c24]Kevin D. Rich, Matthew K. Farrens:
The Decoupled-Style Prefetch Architecture (Research Note). Euro-Par 2000: 989-993 - [c23]Kevin D. Rich, Matthew K. Farrens:
Code Partitioning in Decoupled Compilers. Euro-Par 2000: 1008-1017 - [c22]Michael Haungs, Phil Sallee, Matthew K. Farrens:
Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. HPCA 2000: 241-250 - [c21]Mark Oskin, Frederic T. Chong, Matthew K. Farrens:
HLS: combining statistical and symbolic simulation to guide microprocessor designs. ISCA 2000: 71-82 - [c20]Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens:
Eager writeback - a technique for improving bandwidth utilization. MICRO 2000: 11-21
1990 – 1999
- 1999
- [c19]Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra:
Exploiting ILP in Page-based Intelligent Memory. MICRO 1999: 208-218 - [e2]Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger:
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999. ACM/IEEE Computer Society 1999, ISBN 0-7695-0437-X [contents] - 1998
- [c18]Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens:
Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456 - [c17]Matthew K. Farrens:
The architecture curriculum at UC-Davis. WCAE@ISCA 1998: 25 - 1997
- [j6]Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
Managing data caches using selective cache line replacement. Int. J. Parallel Program. 25(3): 213-242 (1997) - 1996
- [j5]Matthew K. Farrens:
Distributed Decentralized Computing. ACM Comput. Surv. 28(4es): 28 (1996) - [j4]Matthew K. Farrens, Wen-mei W. Hwu:
Guest Editors' Introduction. Int. J. Parallel Program. 24(1): 1-2 (1996) - [j3]Gary S. Tyson, Matthew K. Farrens:
Evaluating the Effects of Predicated Execution on Branch Prediction. Int. J. Parallel Program. 24(2): 159-186 (1996) - 1995
- [c16]Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun:
A modified approach to data cache management. MICRO 1995: 93-103 - 1994
- [j2]Gary S. Tyson, Matthew K. Farrens:
Code scheduling for multiple instruction stream architectures. Int. J. Parallel Program. 22(3): 243-272 (1994) - [c15]Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun:
A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347 - [e1]Hans Mulder, Matthew K. Farrens:
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994. ACM / IEEE Computer Society 1994, ISBN 0-89791-707-3 [contents] - 1993
- [c14]Matthew K. Farrens, Pius Ng, Phil Nico:
A comparision of superscalar and decoupled access/execute architectures. MICRO 1993: 100-103 - [c13]Gary S. Tyson, Matthew K. Farrens:
Techniques for extracting instruction level parallelism on MIMD architectures. MICRO 1993: 128-137 - 1992
- [c12]Matthew K. Farrens, Arvin Park, Allison Woodruff:
CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension. IPPS 1992: 573-577 - [c11]Matthew K. Farrens, Arvin Park, Rob Fanfelle, Pius Ng, Gary S. Tyson:
A partitioned translation lookaside buffer approach to reducing address bandwith. ISCA 1992: 435 - [c10]Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun:
MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196 - [c9]Matthew K. Farrens, Arvin Park, Gary S. Tyson:
Modifying VM hardware to reduce address pin requirements. MICRO 1992: 210-213 - 1991
- [j1]Matthew K. Farrens, Andrew R. Pleszkun:
Implementation of the PIPE Processor. Computer 24(1): 65-69 (1991) - [c8]Matthew K. Farrens, Arvin Park:
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. ISCA 1991: 128-137 - [c7]Matthew K. Farrens, Andrew R. Pleszkun:
Strategies for Achieving Improved Processor Throughput. ISCA 1991: 362-369 - [c6]Jeffrey C. Becker, Arvin Park, Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams. MICRO 1991: 19-24 - [c5]Matthew K. Farrens, Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching. MICRO 1991: 62-68 - [c4]Matthew K. Farrens, Brad Wetmore, Allison Woodruff:
Alleviation of tree saturation in multistage interconnection networks. SC 1991: 400-409 - 1990
- [c3]Arvin Park, Matthew K. Farrens:
Address compression through base register caching. MICRO 1990: 193-199 - [c2]Matthew K. Farrens, Andrew R. Pleszkun:
An evaluation of functional unit lengths for single-chip processors. MICRO 1990: 209-215
1980 – 1989
- 1989
- [c1]Matthew K. Farrens, Andrew R. Pleszkun:
Improving Performance of Small On-Chip Instruction Caches. ISCA 1989: 234-241
Coauthor Index
aka: Christopher J. Nitta
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