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Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/fgcs/SahebiPG25 AU - Sahebi, Amin AU - Procaccini, Marco AU - Giorgi, Roberto TI - HashGrid: An optimized architecture for accelerating graph computing on FPGAs. JO - Future Gener. Comput. Syst. VL - 162 SP - 107497 PY - 2025// DO - 10.1016/J.FUTURE.2024.107497 UR - https://doi.org/10.1016/j.future.2024.107497 ER - TY - JOUR ID - DBLP:journals/jbd/ProcacciniSG24 AU - Procaccini, Marco AU - Sahebi, Amin AU - Giorgi, Roberto TI - A survey of graph convolutional networks (GCNs) in FPGA-based accelerators. JO - J. Big Data VL - 11 IS - 1 SP - 163 PY - 2024/12/ DO - 10.1186/S40537-024-01022-4 UR - https://doi.org/10.1186/s40537-024-01022-4 ER - TY - CPAPER ID - DBLP:conf/hipeac/ProcacciniSBLGG24 AU - Procaccini, Marco AU - Sahebi, Amin AU - Barbone, Marco AU - Luk, Wayne AU - Gaydadjiev, Georgi AU - Giorgi, Roberto TI - Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. BT - 15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2024, January 18, 2024, Munich, Germany SP - 6:1 EP - 6:12 PY - 2024// DO - 10.4230/OASICS.PARMA-DITAM.2024.6 UR - https://doi.org/10.4230/OASIcs.PARMA-DITAM.2024.6 ER - TY - CPAPER ID - DBLP:conf/itadata/Giorgi24 AU - Giorgi, Roberto TI - DF-Threads: A Scalable and Efficient Execution Paradigm for Edge Computing and HPC. BT - Proceedings of the 2nd Special Track on Big Data and High-Performance Computing (BigHPC 2024) co-located with the 3rd Italian Conference on Big Data and Data Science (ITADATA 2024), Pisa, Italy, September 17-19, 2024. SP - 44 EP - 51 PY - 2024// UR - https://ceur-ws.org/Vol-3785/paper123.pdf ER - TY - JOUR ID - DBLP:journals/jbd/SahebiBPLGG23 AU - Sahebi, Amin AU - Barbone, Marco AU - Procaccini, Marco AU - Luk, Wayne AU - Gaydadjiev, Georgi AU - Giorgi, Roberto TI - Distributed large-scale graph processing on FPGAs. JO - J. Big Data VL - 10 IS - 1 SP - 95 PY - 2023/12/ DO - 10.1186/S40537-023-00756-X UR - https://doi.org/10.1186/s40537-023-00756-x ER - TY - JOUR ID - DBLP:journals/softx/MariottiG22 AU - Mariotti, Gianfranco AU - Giorgi, Roberto TI - WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool. JO - SoftwareX VL - 18 SP - 101105 PY - 2022// DO - 10.1016/J.SOFTX.2022.101105 UR - https://doi.org/10.1016/j.softx.2022.101105 ER - TY - CPAPER ID - DBLP:conf/meco/Giorgi22 AU - Giorgi, Roberto TI - Extending Performance and Reliability via Modular FPGA Clusters. BT - 11th Mediterranean Conference on Embedded Computing, MECO 2022, Budva, Montenegro, June 7-10, 2022 SP - 1 PY - 2022// DO - 10.1109/MECO55406.2022.9797208 UR - https://doi.org/10.1109/MECO55406.2022.9797208 ER - TY - JOUR ID - DBLP:journals/dt/FilguerasVMJAMA21 AU - Filgueras, Antonio AU - Vidal, Miquel AU - Mateu, Marc AU - Jiménez-González, Daniel AU - Álvarez, Carlos AU - Martorell, Xavier AU - Ayguadé, Eduard AU - Theodoropoulos, Dimitrios AU - Pnevmatikatos, Dionisios N. AU - Gai, Paolo AU - Garzarella, Stefano AU - Oro, David AU - Hernando, Javier AU - Bettin, Nicola AU - Pomella, Alberto AU - Procaccini, Marco AU - Giorgi, Roberto TI - The AXIOM Project: IoT on Heterogeneous Embedded Platforms. JO - IEEE Des. Test VL - 38 IS - 5 SP - 74 EP - 81 PY - 2021// DO - 10.1109/MDAT.2019.2952335 UR - https://doi.org/10.1109/MDAT.2019.2952335 UR - https://www.wikidata.org/entity/Q114009352 ER - TY - CPAPER ID - DBLP:conf/arcs/GiorgiPS21 AU - Giorgi, Roberto AU - Procaccini, Marco AU - Sahebi, Amin TI - DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model. BT - Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 7-8, 2021, Proceedings SP - 84 EP - 100 PY - 2021// DO - 10.1007/978-3-030-81682-7_6 UR - https://doi.org/10.1007/978-3-030-81682-7_6 ER - TY - CPAPER ID - DBLP:conf/cf/AldinucciAAABCC21 AU - Aldinucci, Marco AU - Agosta, Giovanni AU - Andreini, Antonio AU - Ardagna, Claudio Agostino AU - Bartolini, Andrea AU - Cilardo, Alessandro AU - Cosenza, Biagio AU - Danelutto, Marco AU - Esposito, Roberto AU - Fornaciari, William AU - Giorgi, Roberto AU - Lengani, Davide AU - Montella, Raffaele AU - Olivieri, Mauro AU - Saponara, Sergio AU - Simoni, Daniele AU - Torquati, Massimo TI - The Italian research on HPC key technologies across EuroHPC. BT - CF '21: Computing Frontiers Conference, Virtual Event, Italy, May 11-13, 2021 SP - 178 EP - 184 PY - 2021// DO - 10.1145/3457388.3458508 UR - https://doi.org/10.1145/3457388.3458508 ER - TY - JOUR ID - DBLP:journals/ijrc/GiorgiKP19 AU - Giorgi, Roberto AU - Khalili, Farnam AU - Procaccini, Marco TI - Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). JO - Int. J. Reconfigurable Comput. VL - 2019 SP - 2624938:1 EP - 2624938:18 PY - 2019// DO - 10.1155/2019/2624938 UR - https://doi.org/10.1155/2019/2624938 ER - TY - CPAPER ID - DBLP:conf/date/GiorgiPK19 AU - Giorgi, Roberto AU - Procaccini, Marco AU - Khalili, Farnam TI - AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform. BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019 SP - 480 EP - 485 PY - 2019// DO - 10.23919/DATE.2019.8715168 UR - https://doi.org/10.23919/DATE.2019.8715168 ER - TY - CPAPER ID - DBLP:conf/ieeehpcs/GiorgiP19 AU - Giorgi, Roberto AU - Procaccini, Marco TI - Bridging a Data-Flow Execution Model to a Lightweight Programming Model. BT - 17th International Conference on High Performance Computing & Simulation, HPCS 2019, Dublin, Ireland, July 15-19, 2019 SP - 165 EP - 168 PY - 2019// DO - 10.1109/HPCS48598.2019.9188183 UR - https://doi.org/10.1109/HPCS48598.2019.9188183 ER - TY - CPAPER ID - DBLP:conf/meco/GiorgiBEMR19 AU - Giorgi, Roberto AU - Bettin, Nicola AU - Ermini, Sara AU - Montefoschi, Francesco AU - Rizzo, Antonio TI - An Iris+Voice Recognition System for a Smart Doorbell. BT - 8th Mediterranean Conference on Embedded Computing, MECO 2019, Budva, Montenegro, June 10-14, 2019 SP - 1 EP - 4 PY - 2019// DO - 10.1109/MECO.2019.8760187 UR - https://doi.org/10.1109/MECO.2019.8760187 ER - TY - CPAPER ID - DBLP:conf/meco/GiorgiOEMR19 AU - Giorgi, Roberto AU - Oro, David AU - Ermini, Sara AU - Montefoschi, Francesco AU - Rizzo, Antonio TI - Embedded Face Analysis for Smart Videosurveillance. BT - 8th Mediterranean Conference on Embedded Computing, MECO 2019, Budva, Montenegro, June 10-14, 2019 SP - 1 EP - 4 PY - 2019// DO - 10.1109/MECO.2019.8760200 UR - https://doi.org/10.1109/MECO.2019.8760200 ER - TY - CPAPER ID - DBLP:conf/meco/VerdosciaSG19 AU - Verdoscia, Lorenzo AU - Sahebi, Amin AU - Giorgi, Roberto TI - A Data-Flow Methodology for Accelerating FFT. BT - 8th Mediterranean Conference on Embedded Computing, MECO 2019, Budva, Montenegro, June 10-14, 2019 SP - 1 EP - 4 PY - 2019// DO - 10.1109/MECO.2019.8760044 UR - https://doi.org/10.1109/MECO.2019.8760044 ER - TY - CPAPER ID - DBLP:conf/pdp/GiorgiPK19 AU - Giorgi, Roberto AU - Procaccini, Marco AU - Khalili, Farnam TI - Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment. BT - 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2019, Pavia, Italy, February 13-15, 2019 SP - 422 EP - 429 PY - 2019// DO - 10.1109/EMPDP.2019.8671562 UR - https://doi.org/10.1109/EMPDP.2019.8671562 ER - TY - CPAPER ID - DBLP:conf/rapido/GiorgiPK19 AU - Giorgi, Roberto AU - Procaccini, Marco AU - Khalili, Farnam TI - A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers. BT - Proceedings of the Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO 2019, Valencia, Spain, January 21-23, 2019. SP - 6:1 EP - 6:6 PY - 2019// DO - 10.1145/3300189.3300195 UR - https://doi.org/10.1145/3300189.3300195 ER - TY - CPAPER ID - DBLP:conf/wcae/GiorgiM19 AU - Giorgi, Roberto AU - Mariotti, Gianfranco TI - WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment. BT - Proceedings of the Workshop on Computer Architecture Education, WCAE@ISCA 2019, Phoenix, AZ, USA, June 22, 2019 SP - 3:1 EP - 3:6 PY - 2019// DO - 10.1145/3338698.3338894 UR - https://doi.org/10.1145/3338698.3338894 ER - TY - JOUR ID - DBLP:journals/mam/Giorgi18 AU - Giorgi, Roberto TI - Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump. JO - Microprocess. Microsystems VL - 63 SP - 66 EP - 74 PY - 2018// DO - 10.1016/J.MICPRO.2018.08.005 UR - https://doi.org/10.1016/j.micpro.2018.08.005 ER - TY - CPAPER ID - DBLP:conf/icm2/GiorgiKP18 AU - Giorgi, Roberto AU - Khalili, Farnam AU - Procaccini, Marco TI - Energy Efficiency Exploration on the ZYNQ Ultrascale+. BT - 30th International Conference on Microelectronics, ICM 2018, Sousse, Tunisia, December 16-19, 2018 SP - 48 EP - 54 PY - 2018// DO - 10.1109/ICM.2018.8704092 UR - https://doi.org/10.1109/ICM.2018.8704092 ER - TY - JOUR ID - DBLP:journals/ac/Giorgi17 AU - Giorgi, Roberto TI - Chapter Two - Exploring Future Many-Core Architectures: The TERAFLUX Evaluation Framework. JO - Adv. Comput. VL - 104 SP - 33 EP - 72 PY - 2017// DO - 10.1016/BS.ADCOM.2016.09.002 UR - https://doi.org/10.1016/bs.adcom.2016.09.002 ER - TY - JOUR ID - DBLP:journals/mam/TheodoropoulosM17 AU - Theodoropoulos, Dimitris AU - Mazumdar, Somnath AU - Ayguadé, Eduard AU - Bettin, Nicola AU - Bueno, Javier AU - Ermini, Sara AU - Filgueras, Antonio AU - Jiménez-González, Daniel AU - Álvarez-Martínez, Carlos AU - Martorell, Xavier AU - Montefoschi, Francesco AU - Oro, David AU - Pnevmatikatos, Dionisis N. AU - Rizzo, Antonio AU - Gai, Paolo AU - Garzarella, Stefano AU - Morelli, Bruno AU - Pomella, Alberto AU - Giorgi, Roberto TI - The AXIOM platform for next-generation cyber physical systems. JO - Microprocess. Microsystems VL - 52 SP - 540 EP - 555 PY - 2017// DO - 10.1016/J.MICPRO.2017.05.018 UR - https://doi.org/10.1016/j.micpro.2017.05.018 UR - https://www.wikidata.org/entity/Q57515761 ER - TY - CPAPER ID - DBLP:conf/ecce/RizzoMCGBG17 AU - Rizzo, Antonio AU - Montefoschi, Francesco AU - Caporali, Maurizio AU - Gisondi, Antonio AU - Burresi, Giovanni AU - Giorgi, Roberto TI - Rapid prototyping IoT solutions based on Machine Learning. BT - Proceedings of the European Conference on Cognitive Ergonomics, ECCE 2017, Umeå, Sweden, September 19-22, 2017 SP - 184 EP - 187 PY - 2017// DO - 10.1145/3121283.3121291 UR - https://doi.org/10.1145/3121283.3121291 ER - TY - CPAPER ID - DBLP:conf/meco/Giorgi17 AU - Giorgi, Roberto TI - AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. BT - 6th Mediterranean Conference on Embedded Computing, MECO 2017, Bar, Montenegro, June 11-15, 2017 SP - 1 PY - 2017// DO - 10.1109/MECO.2017.7977117 UR - https://doi.org/10.1109/MECO.2017.7977117 ER - TY - CPAPER ID - DBLP:conf/meco/Giorgi17a AU - Giorgi, Roberto TI - AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. BT - 6th Mediterranean Conference on Embedded Computing, MECO 2017, Bar, Montenegro, June 11-15, 2017 SP - 1 EP - 4 PY - 2017// DO - 10.1109/MECO.2017.7977173 UR - https://doi.org/10.1109/MECO.2017.7977173 ER - TY - JOUR ID - DBLP:journals/ijpp/WeisGFMGU16 AU - Weis, Sebastian AU - Garbade, Arne AU - Fechner, Bernhard AU - Mendelson, Avi AU - Giorgi, Roberto AU - Ungerer, Theo TI - Architectural Support for Fault Tolerance in a Teradevice Dataflow System. JO - Int. J. Parallel Program. VL - 44 IS - 2 SP - 208 EP - 232 PY - 2016// DO - 10.1007/S10766-014-0312-Y UR - https://doi.org/10.1007/s10766-014-0312-y ER - TY - JOUR ID - DBLP:journals/ixda/RizzoBMCG16 AU - Rizzo, Antonio AU - Burresi, Giovanni AU - Montefoschi, Francesco AU - Caporali, Maurizio AU - Giorgi, Roberto TI - Making IoT with UDOO. JO - IxD&A VL - 30 SP - 95 EP - 112 PY - 2016// UR - http://www.mifav.uniroma2.it/inevent/events/idea2010/index.php?s=10&a=10&link=ToC_30_P&link=30_6_abstract ER - TY - CPAPER ID - DBLP:conf/cd/Giorgi16 AU - Giorgi, Roberto TI - Exploring dataflow-based thread level parallelism in cyber-physical systems. BT - Proceedings of the ACM International Conference on Computing Frontiers, CF'16, Como, Italy, May 16-19, 2016 SP - 295 EP - 300 PY - 2016// DO - 10.1145/2903150.2906829 UR - https://doi.org/10.1145/2903150.2906829 ER - TY - CPAPER ID - DBLP:conf/dsd/MazumdarABBEFJA16 AU - Mazumdar, Somnath AU - Ayguadé, Eduard AU - Bettin, Nicola AU - Bueno, Javier AU - Ermini, Sara AU - Filgueras, Antonio AU - Jiménez-González, Daniel AU - Álvarez-Martínez, Carlos AU - Martorell, Xavier AU - Montefoschi, Francesco AU - Oro, David AU - Pnevmatikatos, Dionisios N. AU - Rizzo, Antonio AU - Theodoropoulos, Dimitris AU - Giorgi, Roberto TI - AXIOM: A Hardware-Software Platform for Cyber Physical Systems. BT - 2016 Euromicro Conference on Digital System Design, DSD 2016, Limassol, Cyprus, August 31 - September 2, 2016 SP - 539 EP - 546 PY - 2016// DO - 10.1109/DSD.2016.80 UR - https://doi.org/10.1109/DSD.2016.80 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2016.80 UR - https://www.wikidata.org/entity/Q57515763 ER - TY - BOOK ID - DBLP:series/ccn/MilutinovicSTG15 AU - Milutinovic, Veljko AU - Salom, Jakob AU - Trifunovic, Nemanja AU - Giorgi, Roberto TI - Guide to DataFlow Supercomputing - Basic Concepts, Case Studies, and a Detailed Example T3 - Computer Communications and Networks SP - 1 EP - 122 PY - 2015// PB - Springer DO - 10.1007/978-3-319-16229-4 UR - https://doi.org/10.1007/978-3-319-16229-4 SN - ISBN 978-3-319-16228-7 SN - ISBN 978-3-319-16229-4 ER - TY - JOUR ID - DBLP:journals/fgcs/WesnerSBRPG15 AU - Wesner, Stefan AU - Schubert, Lutz AU - Badia, Rosa M. AU - Rubio, Antonio AU - Paolucci, Pier Stanislao AU - Giorgi, Roberto TI - Special Section on Terascale Computing. JO - Future Gener. Comput. Syst. VL - 53 SP - 88 EP - 89 PY - 2015// DO - 10.1016/J.FUTURE.2015.07.015 UR - https://doi.org/10.1016/j.future.2015.07.015 ER - TY - JOUR ID - DBLP:journals/fgcs/GiorgiS15 AU - Giorgi, Roberto AU - Scionti, Alberto TI - A scalable thread scheduling co-processor based on data-flow principles. JO - Future Gener. Comput. Syst. VL - 53 SP - 100 EP - 108 PY - 2015// DO - 10.1016/J.FUTURE.2014.12.014 UR - https://doi.org/10.1016/j.future.2014.12.014 ER - TY - CPAPER ID - DBLP:conf/cf/HoMSSPG15 AU - Ho, Nam AU - Mondelli, Andrea AU - Scionti, Alberto AU - Solinas, Marco AU - Portero, Antoni AU - Giorgi, Roberto TI - Enhancing an x86_64 multi-core architecture with data-flow execution support. BT - Proceedings of the 12th ACM International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015 SP - 41:1 EP - 41:2 PY - 2015// DO - 10.1145/2742854.2742896 UR - https://doi.org/10.1145/2742854.2742896 ER - TY - CPAPER ID - DBLP:conf/cf/VerdosciaVG15 AU - Verdoscia, Lorenzo AU - Vaccaro, Roberto AU - Giorgi, Roberto TI - A matrix multiplier case study for an evaluation of a configurable dataflow-machine. BT - Proceedings of the 12th ACM International Conference on Computing Frontiers, CF'15, Ischia, Italy, May 18-21, 2015 SP - 63:1 EP - 63:6 PY - 2015// DO - 10.1145/2742854.2747287 UR - https://doi.org/10.1145/2742854.2747287 ER - TY - CPAPER ID - DBLP:conf/dsd/AlvarezABFJMNTP15 AU - Álvarez, Carlos AU - Ayguadé, Eduard AU - Bueno, Javier AU - Filgueras, Antonio AU - Jiménez-González, Daniel AU - Martorell, Xavier AU - Navarro, Nacho AU - Theodoropoulos, Dimitris AU - Pnevmatikatos, Dionisios N. AU - Catani, Davide AU - Scordino, Claudio AU - Gai, Paolo AU - Segura, Carlos AU - Fernández, Carles AU - Oro, David AU - Saeta, Javier Rodríguez AU - Passera, Pierluigi AU - Pomella, Alberto AU - Rizzo, Antonio AU - Giorgi, Roberto TI - The AXIOM Software Layers. BT - 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015 SP - 117 EP - 124 PY - 2015// DO - 10.1109/DSD.2015.52 UR - https://doi.org/10.1109/DSD.2015.52 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2015.52 UR - https://www.wikidata.org/entity/Q57515771 ER - TY - CPAPER ID - DBLP:conf/dsd/MondelliHSSPG15 AU - Mondelli, Andrea AU - Ho, Nam AU - Scionti, Alberto AU - Solinas, Marco AU - Portero, Antoni AU - Giorgi, Roberto TI - Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. BT - 2015 Euromicro Conference on Digital System Design, DSD 2015, Madeira, Portugal, August 26-28, 2015 SP - 526 EP - 529 PY - 2015// DO - 10.1109/DSD.2015.62 UR - https://doi.org/10.1109/DSD.2015.62 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2015.62 ER - TY - CPAPER ID - DBLP:conf/euc/Giorgi15 AU - Giorgi, Roberto TI - Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing. BT - 13th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2013, Porto, Portugal, October 21-23, 2015 SP - 148 EP - 153 PY - 2015// DO - 10.1109/EUC.2015.34 UR - https://doi.org/10.1109/EUC.2015.34 UR - https://doi.ieeecomputersociety.org/10.1109/EUC.2015.34 ER - TY - CPAPER ID - DBLP:conf/meco/BurresiG15 AU - Burresi, Giovanni AU - Giorgi, Roberto TI - A field experience for a vehicle recognition system using magnetic sensors. BT - 4th Mediterranean Conference on Embedded Computing, MECO 2015, Budva, Montenegro, June 14-18, 2015 SP - 178 EP - 181 PY - 2015// DO - 10.1109/MECO.2015.7181897 UR - https://doi.org/10.1109/MECO.2015.7181897 ER - TY - CPAPER ID - DBLP:conf/samos/TheodoropoulosP15 AU - Theodoropoulos, Dimitris AU - Pnevmatikatos, Dionisios N. AU - Álvarez, Carlos AU - Ayguadé, Eduard AU - Bueno, Javier AU - Filgueras, Antonio AU - Jiménez-González, Daniel AU - Martorell, Xavier AU - Navarro, Nacho AU - Segura, Carlos AU - Fernández, Carles AU - Oro, David AU - Saeta, Javier Rodríguez AU - Gai, Paolo AU - Rizzo, Antonio AU - Giorgi, Roberto TI - The AXIOM project (Agile, eXtensible, fast I/O Module). BT - 2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2015, Samos, Greece, July 19-23, 2015 SP - 262 EP - 269 PY - 2015// DO - 10.1109/SAMOS.2015.7363684 UR - https://doi.org/10.1109/SAMOS.2015.7363684 UR - https://www.wikidata.org/entity/Q57515772 ER - TY - JOUR ID - DBLP:journals/mam/GiorgiBBCEFFGGGGGKKLLLLMMNPPTUWWZV14 AU - Giorgi, Roberto AU - Badia, Rosa M. AU - Bodin, François AU - Cohen, Albert AU - Evripidou, Paraskevas AU - Faraboschi, Paolo AU - Fechner, Bernhard AU - Gao, Guang R. AU - Garbade, Arne AU - Gayatri, Rahulkumar AU - Girbal, Sylvain AU - Goodman, Daniel AU - Khan, Behram AU - Koliai, Souad AU - Landwehr, Joshua AU - Lê, Nhat Minh AU - Li, Feng AU - Luján, Mikel AU - Mendelson, Avi AU - Morin, Laurent AU - Navarro, Nacho AU - Patejko, Tomasz AU - Pop, Antoniu AU - Trancoso, Pedro AU - Ungerer, Theo AU - Watson, Ian AU - Weis, Sebastian AU - Zuckerman, Stéphane AU - Valero, Mateo TI - TERAFLUX: Harnessing dataflow in next generation teradevices. JO - Microprocess. Microsystems VL - 38 IS - 8 SP - 976 EP - 990 PY - 2014// DO - 10.1016/J.MICPRO.2014.04.001 UR - https://doi.org/10.1016/j.micpro.2014.04.001 UR - https://www.wikidata.org/entity/Q61730828 ER - TY - CPAPER ID - DBLP:conf/educon/BranovicPJGNZ14 AU - Branovic, Irina AU - Popovic, Ranko AU - Jovanovic, Nenad AU - Giorgi, Roberto AU - Nikolic, Bosko AU - Zivkovic, Miodrag TI - Integration of simulators in virtual 3D computer science classroom. BT - 2014 IEEE Global Engineering Education Conference, EDUCON 2014, Istanbul, Turkey, April 3-5, 2014 SP - 1164 EP - 1167 PY - 2014// DO - 10.1109/EDUCON.2014.7096837 UR - https://doi.org/10.1109/EDUCON.2014.7096837 ER - TY - CPAPER ID - DBLP:conf/meco/SciontiKG14 AU - Scionti, Alberto AU - Kavvadias, Stamatios AU - Giorgi, Roberto TI - Dynamic power reduction in self-adaptive embedded systems through benchmark analysis. BT - 3rd Mediterranean Conference on Embedded Computing, MECO 2014, Budva, Montenegro, June 15-19, 2014 SP - 62 EP - 65 PY - 2014// DO - 10.1109/MECO.2014.6862659 UR - https://doi.org/10.1109/MECO.2014.6862659 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/GiorgiF14 AU - Giorgi, Roberto AU - Faraboschi, Paolo TI - An Introduction to DF-Threads and their Execution Model. BT - 26th IEEE International Symposium on Computer Architecture and High Performance Computing Workshop, SBAC-PAD Workshop 2014, Paris, France, October 22-24, 2014 SP - 60 EP - 65 PY - 2014// DO - 10.1109/SBAC-PADW.2014.30 UR - https://doi.org/10.1109/SBAC-PADW.2014.30 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PADW.2014.30 ER - TY - CPAPER ID - DBLP:conf/dsd/SolinasBBCEFFGGGGKKLLMMNPTUVWWZG13 AU - Solinas, Marco AU - Badia, Rosa M. AU - Bodin, François AU - Cohen, Albert AU - Evripidou, Paraskevas AU - Faraboschi, Paolo AU - Fechner, Bernhard AU - Gao, Guang R. AU - Garbade, Arne AU - Girbal, Sylvain AU - Goodman, Daniel AU - Khan, Behram AU - Koliai, Souad AU - Li, Feng AU - Luján, Mikel AU - Morin, Laurent AU - Mendelson, Avi AU - Navarro, Nacho AU - Pop, Antoniu AU - Trancoso, Pedro AU - Ungerer, Theo AU - Valero, Mateo AU - Weis, Sebastian AU - Watson, Ian AU - Zuckerman, Stéphane AU - Giorgi, Roberto TI - The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. BT - 2013 Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, CA, USA, September 4-6, 2013 SP - 272 EP - 279 PY - 2013// DO - 10.1109/DSD.2013.39 UR - https://doi.org/10.1109/DSD.2013.39 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2013.39 UR - https://www.wikidata.org/entity/Q61730846 ER - TY - CPAPER ID - DBLP:conf/cases/WongCKKPSGK12 AU - Wong, Stephan AU - Carro, Luigi AU - Kavvadias, Stamatios AU - Keramidas, Georgios AU - Papariello, Francesco AU - Scordino, Claudio AU - Giorgi, Roberto AU - Kaxiras, Stefanos TI - Embedded reconfigurable architectures. BT - Proceedings of the 15th International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2012, part of the Eighth Embedded Systems Week, ESWeek 2012, Tampere, Finland, October 7-12, 2012 SP - 213 EP - 214 PY - 2012// DO - 10.1145/2380403.2380444 UR - https://doi.org/10.1145/2380403.2380444 ER - TY - CPAPER ID - DBLP:conf/cf/Giorgi12 AU - Giorgi, Roberto TI - TERAFLUX: exploiting dataflow parallelism in teradevices. BT - Proceedings of the Computing Frontiers Conference, CF'12, Caligari, Italy - May 15 - 17, 2012 SP - 303 EP - 304 PY - 2012// DO - 10.1145/2212908.2212959 UR - https://doi.org/10.1145/2212908.2212959 ER - TY - CPAPER ID - DBLP:conf/springsim/PorteroSYFCCGWUG12 AU - Portero, Antoni AU - Scionti, Alberto AU - Yu, Zhibin AU - Faraboschi, Paolo AU - Concatto, Caroline AU - Carro, Luigi AU - Garbade, Arne AU - Weis, Sebastian AU - Ungerer, Theo AU - Giorgi, Roberto TI - Simulating the future kilo-x86-64 core processors and their infrastructure. BT - 2012 Spring Simulation Multiconference, SpringSim '12, Orlando, FL, USA - March 26-29, 2012, Proceedings of the 45th Annual Simulation Symposium SP - 9 PY - 2012// UR - http://dl.acm.org/citation.cfm?id=2331760 ER - TY - CPAPER ID - DBLP:journals/procedia/PorteroYG11 AU - Portero, Antoni AU - Yu, Zhibin AU - Giorgi, Roberto TI - TERAFLUX: Exploiting Tera-device Computing Challenges. BT - Proceedings of the 2nd European Future Technologies Conference and Exhibition, FET 2011, Budapest, Hungary, May 4-6, 2011 SP - 146 EP - 147 PY - 2011// DO - 10.1016/J.PROCS.2011.09.081 UR - https://doi.org/10.1016/j.procs.2011.09.081 ER - TY - CPAPER ID - DBLP:conf/iscas/AliotoBG10 AU - Alioto, Massimo AU - Bennati, Paolo AU - Giorgi, Roberto TI - Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. BT - International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France SP - 37 EP - 40 PY - 2010// DO - 10.1109/ISCAS.2010.5537105 UR - https://doi.org/10.1109/ISCAS.2010.5537105 ER - TY - CPAPER ID - DBLP:conf/cisis/GiorgiPP09 AU - Giorgi, Roberto AU - Popovic, Zdravko AU - Puzovic, Nikola TI - Introducing Hardware TLP Support in the Cell Processor. BT - 2009 International Conference on Complex, Intelligent and Software Intensive Systems, CISIS 2009, Fukuoka, Japan, March 16-19, 2009 SP - 657 EP - 662 PY - 2009// DO - 10.1109/CISIS.2009.177 UR - https://doi.org/10.1109/CISIS.2009.177 UR - https://doi.ieeecomputersociety.org/10.1109/CISIS.2009.177 ER - TY - CPAPER ID - DBLP:conf/ipps/GiorgiPP09 AU - Giorgi, Roberto AU - Popovic, Zdravko AU - Puzovic, Nikola TI - Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. BT - 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009 SP - 1 EP - 8 PY - 2009// DO - 10.1109/IPDPS.2009.5161111 UR - https://doi.org/10.1109/IPDPS.2009.5161111 UR - https://doi.ieeecomputersociety.org/10.1109/IPDPS.2009.5161111 ER - TY - CPAPER ID - DBLP:conf/ispdc/StavrouPNPETPG09 AU - Stavrou, Kyriakos AU - Pavlou, Demos AU - Nikolaides, Marios AU - Petrides, Panayiotis AU - Evripidou, Paraskevas AU - Trancoso, Pedro AU - Popovic, Zdravko AU - Giorgi, Roberto TI - Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. BT - Eighth International Symposium on Parallel and Distributed Computing, ISPDC 2009, Lisbon, Portugal, June 30-July 4 2009 SP - 107 EP - 114 PY - 2009// DO - 10.1109/ISPDC.2009.35 UR - https://doi.org/10.1109/ISPDC.2009.35 UR - https://doi.ieeecomputersociety.org/10.1109/ISPDC.2009.35 ER - TY - CPAPER ID - DBLP:conf/samos/GiorgiPP09 AU - Giorgi, Roberto AU - Popovic, Zdravko AU - Puzovic, Nikola TI - Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. BT - Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings SP - 78 EP - 87 PY - 2009// DO - 10.1007/978-3-642-03138-0_9 UR - https://doi.org/10.1007/978-3-642-03138-0_9 ER - TY - CHAP ID - DBLP:books/sp/koc09/BartoliniGM09 AU - Bartolini, Sandro AU - Giorgi, Roberto AU - Martinelli, Enrico TI - Instruction Set Extensions for Cryptographic Applications. BT - Cryptographic Engineering SP - 191 EP - 233 PY - 2009// DO - 10.1007/978-0-387-71817-0_9 UR - https://doi.org/10.1007/978-0-387-71817-0_9 ER - TY - CONF ID - DBLP:conf/medea/2009 ED - Bartolini, Sandro ED - Foglia, Pierfrancesco ED - Giorgi, Roberto ED - Prete, Cosimo Antonio TI - Proceedings of the 10th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '09, Raleigh, North Carolina, USA, September 13, 2009 PY - 2009// PB - ACM DO - 10.1145/1621960 UR - https://doi.org/10.1145/1621960 SN - ISBN 978-1-60558-830-8 ER - TY - JOUR ID - DBLP:journals/tc/BartoliniBGM08 AU - Bartolini, Sandro AU - Branovic, Irina AU - Giorgi, Roberto AU - Martinelli, Enrico TI - Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). JO - IEEE Trans. Computers VL - 57 IS - 5 SP - 672 EP - 685 PY - 2008// DO - 10.1109/TC.2007.70832 UR - https://doi.org/10.1109/TC.2007.70832 UR - http://doi.ieeecomputersociety.org/10.1109/TC.2007.70832 ER - TY - CPAPER ID - DBLP:conf/dsd/GiorgiPPAJ08 AU - Giorgi, Roberto AU - Popovic, Zdravko AU - Puzovic, Nikola AU - Azevedo, Arnaldo AU - Juurlink, Ben H. H. TI - Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. BT - 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008 SP - 189 EP - 194 PY - 2008// DO - 10.1109/DSD.2008.93 UR - https://doi.org/10.1109/DSD.2008.93 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2008.93 ER - TY - CPAPER ID - DBLP:conf/dsd/GiorgiB08 AU - Giorgi, Roberto AU - Bennati, Paolo TI - Reducing Leakage through Filter Cache. BT - 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008 SP - 334 EP - 341 PY - 2008// DO - 10.1109/DSD.2008.123 UR - https://doi.org/10.1109/DSD.2008.123 UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2008.123 ER - TY - CPAPER ID - DBLP:conf/sac/GiorgiB08 AU - Giorgi, Roberto AU - Bennati, Paolo TI - Filtering drowsy instruction cache to achieve better efficiency. BT - Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008 SP - 1554 EP - 1555 PY - 2008// DO - 10.1145/1363686.1364050 UR - https://doi.org/10.1145/1363686.1364050 ER - TY - CONF ID - DBLP:conf/medea/2008 ED - Foglia, Pierfrancesco ED - Prete, Cosimo Antonio ED - Bartolini, Sandro ED - Giorgi, Roberto TI - Proceedings of the 9th workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '08, Toronto, Canada, October 26, 2008 PY - 2008// PB - ACM DO - 10.1145/1509084 UR - https://doi.org/10.1145/1509084 SN - ISBN 978-1-60558-243-6 ER - TY - CPAPER ID - DBLP:conf/medea/GiorgiB07 AU - Giorgi, Roberto AU - Bennati, Paolo TI - Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. BT - Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007 SP - 97 EP - 104 PY - 2007// DO - 10.1145/1327171.1327183 UR - https://doi.org/10.1145/1327171.1327183 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/GiorgiPP07 AU - Giorgi, Roberto AU - Popovic, Zdravko AU - Puzovic, Nikola TI - DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. BT - 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil SP - 263 EP - 270 PY - 2007// DO - 10.1109/SBAC-PAD.2007.27 UR - https://doi.org/10.1109/SBAC-PAD.2007.27 UR - https://doi.ieeecomputersociety.org/10.1109/SBAC-PAD.2007.27 ER - TY - CONF ID - DBLP:conf/medea/2007 ED - Foglia, Pierfrancesco ED - Prete, Cosimo Antonio ED - Bartolini, Sandro ED - Giorgi, Roberto TI - Proceedings of the 2007 workshop on MEmory performance - DEaling with Applications, systems and architecture, MEDEA '07, Brasov, Romania, September 16, 2007 PY - 2007// PB - ACM DO - 10.1145/1327171 UR - https://doi.org/10.1145/1327171 SN - ISBN 978-1-59593-807-7 ER - TY - JOUR ID - DBLP:journals/jec/BartoliniG06 AU - Bartolini, Sandro AU - Giorgi, Roberto TI - Issues in Embedded Single-Chip Multicore Architectures. JO - J. Embed. Comput. VL - 2 IS - 2 SP - 137 EP - 139 PY - 2006// UR - http://content.iospress.com/articles/journal-of-embedded-computing/jec00022 ER - TY - JOUR ID - DBLP:journals/sigarch/BartoliniFGP06 AU - Bartolini, Sandro AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Memory performance: dealing with applications, systems and architecture. JO - SIGARCH Comput. Archit. News VL - 34 IS - 1 SP - 1 EP - 2 PY - 2006// DO - 10.1145/1147349.1147352 UR - https://doi.org/10.1145/1147349.1147352 ER - TY - JOUR ID - DBLP:journals/jpdc/FogliaGP05 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. JO - J. Parallel Distributed Comput. VL - 65 IS - 3 SP - 289 EP - 306 PY - 2005// DO - 10.1016/J.JPDC.2004.10.003 UR - https://doi.org/10.1016/j.jpdc.2004.10.003 ER - TY - JOUR ID - DBLP:journals/ijhpcn/FogliaGP04 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Speeding-up multiprocessors running DBMS workloads through coherence protocols. JO - Int. J. High Perform. Comput. Netw. VL - 1 IS - 1/2/3 SP - 17 EP - 32 PY - 2004// DO - 10.1504/IJHPCN.2004.007562 UR - https://doi.org/10.1504/IJHPCN.2004.007562 ER - TY - JOUR ID - DBLP:journals/sigarch/BranovicGM04 AU - Branovic, Irina AU - Giorgi, Roberto AU - Martinelli, Enrico TI - A workload characterization of elliptic curve cryptography methods in embedded environments. JO - SIGARCH Comput. Archit. News VL - 32 IS - 3 SP - 27 EP - 34 PY - 2004// DO - 10.1145/1024295.1024299 UR - https://doi.org/10.1145/1024295.1024299 ER - TY - CPAPER ID - DBLP:conf/sbac-pad/BartoliniBGM04 AU - Bartolini, Sandro AU - Branovic, Irina AU - Giorgi, Roberto AU - Martinelli, Enrico TI - A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. BT - 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil SP - 238 EP - 245 PY - 2004// DO - 10.1109/SBAC-PAD.2004.5 UR - https://doi.org/10.1109/SBAC-PAD.2004.5 UR - https://doi.ieeecomputersociety.org/10.1109/CAHPC.2004.5 ER - TY - CPAPER ID - DBLP:conf/wcae/BranovicGM04 AU - Branovic, Irina AU - Giorgi, Roberto AU - Martinelli, Enrico TI - WebMIPS: a new web-based MIPS simulation environment for computer architecture education. BT - Proceedings of the 2004 workshop on Computer architecture education - Held in conjunction with the 31st International Symposium on Computer Architecture, WCAE@ISCA 2004, Munich, Germany, June 19, 2004 SP - 19 PY - 2004// DO - 10.1145/1275571.1275596 UR - https://doi.org/10.1145/1275571.1275596 ER - TY - CONF ID - DBLP:conf/medea/2004 ED - Bartolini, Sandro ED - Foglia, Pierfrancesco ED - Giorgi, Roberto ED - Prete, Cosimo Antonio TI - Proceedings of the 2004 workshop on MEmory performance - DEaling with Applications , systems and architecture, MEDEA '04, Antibes Juan-les-Pins, France, September 29 - October 3, 2004 PY - 2004// PB - ACM DO - 10.1145/1152922 UR - https://doi.org/10.1145/1152922 ER - TY - CPAPER ID - DBLP:conf/networking/FogliaGP02 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. BT - Web Engineering and Peer-to-Peer Computing, NETWORKING 2002 Workshops, Pisa, Italy, May 19-24, 2002, Revised Papers SP - 134 EP - 146 PY - 2002// DO - 10.1007/3-540-45745-3_12 UR - https://doi.org/10.1007/3-540-45745-3_12 ER - TY - CPAPER ID - DBLP:conf/wcae/BranovicGP02 AU - Branovic, Irina AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Web-based training on computer architecture: the case for JCachesim. BT - Proceedings of the 2002 workshop on Computer architecture education - Held in conjunction with the 29th International Symposium on Computer Architecture, WCAE@ISCA 2002, Anchorage, Alaska, USA, May 26, 2002 SP - 10 PY - 2002// DO - 10.1145/1275462.1275477 UR - https://doi.org/10.1145/1275462.1275477 ER - TY - JOUR ID - DBLP:journals/sigarch/BartoliniGPPV01 AU - Bartolini, Sandro AU - Giorgi, Roberto AU - Protic, Jelica AU - Prete, Cosimo Antonio AU - Valero, Mateo TI - Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. JO - SIGARCH Comput. Archit. News VL - 29 IS - 5 SP - 9 EP - 12 PY - 2001// DO - 10.1145/563647.563651 UR - https://doi.org/10.1145/563647.563651 ER - TY - JOUR ID - DBLP:journals/tc/KaviGA01 AU - Kavi, Krishna M. AU - Giorgi, Roberto AU - Arul, Joseph TI - Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. JO - IEEE Trans. Computers VL - 50 IS - 8 SP - 834 EP - 846 PY - 2001// DO - 10.1109/12.947003 UR - https://doi.org/10.1109/12.947003 UR - http://doi.ieeecomputersociety.org/10.1109/12.947003 ER - TY - CPAPER ID - DBLP:conf/ISCApdcs/KaviAG01 AU - Kavi, Krishna M. AU - Arul, Joseph AU - Giorgi, Roberto TI - Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. BT - Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA SP - 365 EP - 371 PY - 2001// ER - TY - CPAPER ID - DBLP:conf/hicss/FogliaGP01 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. BT - 34th Annual Hawaii International Conference on System Sciences (HICSS-34), January 3-6, 2001, Maui, Hawaii, USA PY - 2001// DO - 10.1109/HICSS.2001.927077 UR - https://doi.org/10.1109/HICSS.2001.927077 UR - https://doi.ieeecomputersociety.org/10.1109/HICSS.2001.927077 ER - TY - JOUR ID - DBLP:journals/jucs/KaviAG00 AU - Kavi, Krishna M. AU - Arul, Joseph AU - Giorgi, Roberto TI - Execution and Cache Performance of the Scheduled Dataflow Architecture. JO - J. Univers. Comput. Sci. VL - 6 IS - 10 SP - 948 EP - 967 PY - 2000// DO - 10.3217/JUCS-006-10-0948 UR - https://doi.org/10.3217/jucs-006-10-0948 ER - TY - CPAPER ID - DBLP:conf/hicss/FogliaGP00 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Performance Analysis of Electronic Commerce Multiprocessor Server. BT - 33rd Annual Hawaii International Conference on System Sciences (HICSS-33), 4-7 January, 2000, Maui, Hawaii, USA PY - 2000// DO - 10.1109/HICSS.2000.926880 UR - https://doi.org/10.1109/HICSS.2000.926880 UR - https://doi.ieeecomputersociety.org/10.1109/HICSS.2000.926880 ER - TY - JOUR ID - DBLP:journals/tpds/GiorgiP99 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. JO - IEEE Trans. Parallel Distributed Syst. VL - 10 IS - 7 SP - 742 EP - 763 PY - 1999// DO - 10.1109/71.780868 UR - https://doi.org/10.1109/71.780868 UR - http://doi.ieeecomputersociety.org/10.1109/71.780868 ER - TY - CPAPER ID - DBLP:conf/hipc/FogliaGP99 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Process Migration Effects on Memory Performance of Multiprocessor. BT - High Performance Computing - HiPC'99, 6th International Conference, Calcutta, India, December 17-20, 1999, Proceedings SP - 133 EP - 142 PY - 1999// DO - 10.1007/978-3-540-46642-0_19 UR - https://doi.org/10.1007/978-3-540-46642-0_19 ER - TY - CPAPER ID - DBLP:conf/hicss/FogliaGP98 AU - Foglia, Pierfrancesco AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - Analysis of Sharing Overhead in Shared Memory Multiprocessors. BT - Thirty-First Annual Hawaii International Conference on System Sciences, Kohala Coast, Hawaii, USA, January 6-9, 1998 SP - 776 EP - 777 PY - 1998// DO - 10.1109/HICSS.1998.649284 UR - https://doi.org/10.1109/HICSS.1998.649284 UR - https://doi.ieeecomputersociety.org/10.1109/HICSS.1998.649284 ER - TY - CPAPER ID - DBLP:conf/wcae/GiorgiP98 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio TI - An educational environment for designing and performance tuning of embedded systems. BT - Proceedings of the 1998 workshop on Computer architecture education, WCAE@ISCA 1998, Barcelona, Spain, June 1998 SP - 29 PY - 1998// DO - 10.1145/1275182.1275211 UR - https://doi.org/10.1145/1275182.1275211 ER - TY - JOUR ID - DBLP:journals/ieeecc/GiorgiPPR97 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio AU - Prina, Gianpaolo AU - Ricciardi, Luigi M. TI - Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. JO - IEEE Concurrency VL - 5 IS - 4 SP - 54 EP - 68 PY - 1997// DO - 10.1109/4434.641627 UR - https://doi.org/10.1109/4434.641627 UR - http://doi.ieeecomputersociety.org/10.1109/4434.641627 ER - TY - CPAPER ID - DBLP:conf/hicss/GiorgiPPR97 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio AU - Prina, Gianpaolo AU - Ricciardi, Luigi M. TI - A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. BT - 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 7-10 January 1997, Maui, Hawaii, USA SP - 266 EP - 275 PY - 1997// DO - 10.1109/HICSS.1997.667272 UR - https://doi.org/10.1109/HICSS.1997.667272 UR - https://doi.ieeecomputersociety.org/10.1109/HICSS.1997.667272 ER - TY - CPAPER ID - DBLP:conf/mse/GiorgiPP97 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio AU - Prina, Gianpaolo TI - Cache memory design for embedded systems based on program locality analysis. BT - 1997 IEEE International Conference on Microelectronic Systems Education, MSE '97, Arlington, VA, USA, July 21-23, 1997 SP - 16 EP - 18 PY - 1997// DO - 10.1109/MSE.1997.612528 UR - https://doi.org/10.1109/MSE.1997.612528 UR - https://doi.ieeecomputersociety.org/10.1109/MSE.1997.612528 ER - TY - CPAPER ID - DBLP:conf/euromicro/GiorgiPRP96 AU - Giorgi, Roberto AU - Prete, Cosimo Antonio AU - Ricciardi, Luigi M. AU - Prina, Gianpaolo TI - A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. BT - 22rd EUROMICRO Conference '96, Beyond 2000: Hardware and Software Design Strategies, September 2-5, 1996, Prague, Czech Republic SP - 207 EP - 214 PY - 1996// DO - 10.1109/EURMIC.1996.546384 UR - https://doi.org/10.1109/EURMIC.1996.546384 UR - https://doi.ieeecomputersociety.org/10.1109/EURMIC.1996.546384 ER -