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2024
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Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS 2024: 104-109
2023
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Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT 2023: 1-6
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Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS 2023: 1-7
2022
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Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI 2022: 394-397

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