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Link to original content: https://dblp.org/pid/325/8145.rss
dblp: Minjae Jeong https://dblp.org/pid/325/8145.html dblp person page RSS feed Fri, 11 Oct 2024 17:28:16 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Minjae Jeonghttps://dblp.org/pid/325/8145.html14451 Uncertainty-Aware Diffusion-Based Adversarial Attack for Realistic Colonoscopy Image Synthesis.https://doi.org/10.1007/978-3-031-72114-4_62, , , :
Uncertainty-Aware Diffusion-Based Adversarial Attack for Realistic Colonoscopy Image Synthesis. MICCAI (9) : 647-658]]>
https://dblp.org/rec/conf/miccai/JeongCJK24Mon, 01 Jan 2024 00:00:00 +0100
Multi-resolution Spectral Coherence for Graph Generation with Score-based Diffusion.http://papers.nips.cc/paper_files/paper/2023/hash/427f20d90386fd27804f1831d6a3d48f-Abstract-Conference.html, , , , :
Multi-resolution Spectral Coherence for Graph Generation with Score-based Diffusion. NeurIPS ]]>
https://dblp.org/rec/conf/nips/ChoJJAK23Sun, 01 Jan 2023 00:00:00 +0100
Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA.https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185417, , , , , , , , , , , , , :
Breakthrough Design Technology Co-optimization using BSPDN and Standard Cell Variants for Maximizing Block-level PPA. VLSI Technology and Circuits : 1-2]]>
https://dblp.org/rec/conf/vlsit/LeeJJDYYJLHPKKK23Sun, 01 Jan 2023 00:00:00 +0100
Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process.https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830450, , , , , , , , , , , , , , , , , , :
Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. VLSI Technology and Circuits : 363-364]]>
https://dblp.org/rec/conf/vlsit/YangJLSKYYKKJPA22Sat, 01 Jan 2022 00:00:00 +0100