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dblp: Toshinobu Shinbo

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Toshinobu Shinbo

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1990 – 1999

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1996
[j2]
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  dblp key:
  - journals/jssc/MizunoMOSOIIK96
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  persistent URL:
  - https://dblp.org/rec/journals/jssc/MizunoMOSOIIK96
Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure:
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31(11): 1618-1624 (1996)
1995
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Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome:
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30(3): 251-257 (1995)

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