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Xu Cheng 0002 Fudan University, State Key Laboratory of ASIC and System, Shanghai, China Cypress Semiconductor Corporation, Ireland Design Centre, Ireland University College Cork, Tyndall National Institute, Ireland https://orcid.org/0000-0002-0314-0178 Xu Cheng Xu Cheng 0001 Peking University, Microprocessor Research and Development Center, Beijing, China https://orcid.org/0000-0002-5544-8852 Xu Cheng 0003 Nanjing University of Information Science and Technology, School of Computer and Software, Nanjing, China Nanjing Marine Radar Institute, China Southeast University, School of Information Science and Engineering, Nanjing, China https://scholar.google.com/citations?user=roGixUIAAAAJ https://orcid.org/0000-0003-2355-9010 Xu Cheng 0004 Simon Fraser University, Burnaby, BC, Canada Xu Cheng 0005 Shanghai Jiao Tong University, Shanghai, China https://cx1208.github.io/ChengXuSJTU.github.io/ https://scholar.google.com/citations?user=v8AKaXMAAAAJ https://orcid.org/0000-0002-3317-1020

Zhen Li Jing Wang Man-Kay Law Sijun Du Junrui Liang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng Zhiyuan Chen 0002 Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT. 2248-2259 2024 July 59 IEEE J. Solid State Circuits 7 https://doi.org/10.1109/JSSC.2023.3341865 db/journals/jssc/jssc59.html#LiWLDLCHZC24

Yongliang Zhang Yitong Rong Xuyang Duan Zhen Yang Qiang Li Ziyu Guo Xu Cheng 0002 Xiaoyang Zeng Jun Han 0003 An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition. 320-333 2024 January 71 IEEE Trans. Circuits Syst. I Regul. Pap. 1 https://doi.org/10.1109/TCSI.2023.3320175 db/journals/tcasI/tcasI71.html#ZhangRDYLGCZH24

Yuanyuan Han Xu Cheng 0002 Xiaoyong Xue Jun Han 0003 Jiawei Xu 0001 Xiaoyang Zeng SET Tolerable SRAM Hardened by DMR Circuit With Feedback-Split-Gate Voter and High-Speed Hierarchical Structure. 1416-1420 2024 March 71 IEEE Trans. Circuits Syst. II Express Briefs 3 https://doi.org/10.1109/TCSII.2023.3324036 db/journals/tcasII/tcasII71.html#HanCXHXZ24

Jiawei Wang Zhao Gao Xu Cheng 0002 Jue Wang Zhen Li Jun Han 0003 Xiaoyang Zeng A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique. 1859-1863 2024 April 71 IEEE Trans. Circuits Syst. II Express Briefs 4 https://doi.org/10.1109/TCSII.2023.3335987 db/journals/tcasII/tcasII71.html#WangGCWLHZ24

Song Wang Xu Cheng 0002 Ziyu Guo Jun Han 0003 A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity. 105778 2023 136 Microelectron. J. https://doi.org/10.1016/j.mejo.2023.105778 db/journals/mj/mj136.html#Wang0G023

Yan Liu Yan Li 0084 Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency for Harsh Environments Applications. 1639-1648 2023 April 70 IEEE Trans. Circuits Syst. I Regul. Pap. 4 https://doi.org/10.1109/TCSI.2023.3237706 db/journals/tcasI/tcasI70.html#LiuLCHZ23

Yan Li 0084 Chao Chen Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng DMBF: Design Metrics Balancing Framework for Soft-Error-Tolerant Digital Circuits Through Bayesian Optimization. 4015-4027 2023 October 70 IEEE Trans. Circuits Syst. I Regul. Pap. 10 https://doi.org/10.1109/TCSI.2023.3302341 db/journals/tcasI/tcasI70.html#LiCCHZ23

Baijie Zhang Jiawei Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators. 5242-5253 2023 December 70 IEEE Trans. Circuits Syst. I Regul. Pap. 12 https://doi.org/10.1109/TCSI.2023.3318399 db/journals/tcasI/tcasI70.html#ZhangWCHZ23

Zhen Li Zhiyuan Chen 0002 Man-Kay Law Sijun Du Xu Cheng 0002 Xiaoyang Zeng Jun Han 0003 A Self Bias-flip Piezoelectric Energy Harvester Array without External Energy Reservoirs achieving 488% Improvement with 4-Ratio Switched-PEH DC-DC Converter. 1-2 2023 CICC https://doi.org/10.1109/CICC57935.2023.10121219 conf/cicc/2023 db/conf/cicc/cicc2023.html#LiCLDCZH23 Shaohang Chu Yan Li 0084 Xu Cheng 0002 Xiaoyang Zeng An Improved Multi-Objective Optimization Framework for Soft-Error Immune Circuits. 481-484 2022 APCCAS https://doi.org/10.1109/APCCAS55924.2022.10090258 conf/apccas/2022 db/conf/apccas/apccas2022.html#ChuLCZ22 Baijie Zhang Jue Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased Reference Generators. 848-851 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937680 conf/iscas/2022 db/conf/iscas/iscas2022.html#ZhangW00Z22 Jing Wang Zhiyuan Chen 0002 Junrui Liang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric Energy Harvesting System Using Shared Capacitors. 2768-2772 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937938 conf/iscas/2022 db/conf/iscas/iscas2022.html#WangCL00Z22 Min Li Jue Wang Xu Cheng 0002 Xiaoyang Zeng A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback Noise. 2876-2880 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937495 conf/iscas/2022 db/conf/iscas/iscas2022.html#LiWCZ22 Jiawei Wang Jue Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear Calibration. 2933-2937 2022 ISCAS https://doi.org/10.1109/ISCAS48785.2022.9937746 conf/iscas/2022 db/conf/iscas/iscas2022.html#WangWC0Z22

Jue Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC. 105007 2021 110 Microelectron. J. https://doi.org/10.1016/j.mejo.2021.105007 db/journals/mj/mj110.html#WangCHZ21

Weizhen Wang Jun Han 0003 Xu Cheng 0002 Xiaoyang Zeng An energy-efficient crypto-extension design for RISC-V. 105165 2021 115 Microelectron. J. https://doi.org/10.1016/j.mejo.2021.105165 db/journals/mj/mj115.html#WangHCZ21

Yong-Liang Zhang Qiang Li Hui Zhang Wei-Zhen Wang Jun Han 0003 Xiaoyang Zeng Xu Cheng 0002 A 28 nm, 397 μW real-time dynamic gesture recognition chip based on RISC-V processor. 105219 2021 116 Microelectron. J. https://doi.org/10.1016/j.mejo.2021.105219 db/journals/mj/mj116.html#ZhangLZWHZC21

Yuanyuan Han Tongde Li Xu Cheng 0002 Liang Wang 0024 Jun Han 0003 Yuanfu Zhao Xiaoyang Zeng Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology. 2962-2975 2021 68 IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2021.3074699 db/journals/tcasI/tcasI68.html#HanLCWHZZ21

Chiyu Tan Yan Li 0084 Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework. 3044-3057 2021 68 IEEE Trans. Circuits Syst. I Regul. Pap. 7 https://doi.org/10.1109/TCSI.2021.3076185 db/journals/tcasI/tcasI68.html#TanLCHZ21

Jinrong Li Jue Wang Xu Cheng 0002 Yicheng Zeng Xiaoyang Zeng A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process. 1-4 2021 ASICON https://doi.org/10.1109/ASICON52560.2021.9620302 conf/asicon/2021 db/conf/asicon/asicon2021.html#LiW0ZZ21 Hui Zhang Zhaojie Li Heqing Yang Xu Cheng 0002 Xiaoyang Zeng A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network. 1-4 2021 ASICON https://doi.org/10.1109/ASICON52560.2021.9620305 conf/asicon/2021 db/conf/asicon/asicon2021.html#ZhangLYCZ21 Jue Wang Zhenyu Yang Jiawei Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng A Synthesizable 0.0060mm<sup>2</sup> VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme. 1-3 2021 A-SSCC https://doi.org/10.1109/A-SSCC53895.2021.9634735 conf/asscc/2021 db/conf/asscc/asscc2021.html#WangYWCHZ21

Guozhu Xin Jun Han 0003 Tianyu Yin Yuchao Zhou Jianwei Yang Xu Cheng 0002 Xiaoyang Zeng VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture. 2672-2684 2020 67-I IEEE Trans. Circuits Syst. I Regul. Pap. 8 https://doi.org/10.1109/TCSI.2020.2983185 db/journals/tcas/tcasI67.html#XinHYZYCZ20

Yan Li 0084 Xu Cheng 0002 Chiyu Tan Jun Han 0003 Yuanfu Zhao Liang Wang 0024 Tongde Li Mehdi B. Tahoori Xiaoyang Zeng A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in 28nm CMOS for Spaceborne Application. 1619-1623 2020 67-II IEEE Trans. Circuits Syst. II Express Briefs 9 https://doi.org/10.1109/TCSII.2020.3013338 db/journals/tcas/tcasII67.html#LiCTHZWLTZ20

Yuanyuan Han Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. 1089-1093 2020 28 IEEE Trans. Very Large Scale Integr. Syst. 4 https://doi.org/10.1109/TVLSI.2019.2961736 db/journals/tvlsi/tvlsi28.html#HanCHZ20

Yan Li 0084 Xiaoyoung Zeng Zhengqi Gao Liyu Lin Jun Tao 0001 Jun Han 0003 Xu Cheng 0002 Mehdi B. Tahoori Xiaoyang Zeng Exploring a Bayesian Optimization Framework Compatible with Digital Standard Flow for Soft-Error-Tolerant Circuit. 1-6 2020 DAC https://doi.org/10.1109/DAC18072.2020.9218696 conf/dac/2020 db/conf/dac/dac2020.html#LiZGLTH0TZ20 Xu Cheng 0002 Jue Wang Jun Han 0003 Xiaoyang Zeng Design Methodology of Clock Polarity Inversion Technique for Frequency Dividers. 1-5 2020 ISCAS https://doi.org/10.1109/ISCAS45731.2020.9180450 conf/iscas/2020 db/conf/iscas/iscas2020.html#0002W0Z20 Jue Wang Xu Cheng 0002 Jun Han 0003 Xiaoyang Zeng A Synthesis Friendly VCO-Based Delta-Sigma ADC with Process Variation Tolerance. 1-5 2020 ISCAS https://doi.org/10.1109/ISCAS45731.2020.9180939 conf/iscas/2020 db/conf/iscas/iscas2020.html#WangCHZ20

Li Li 0038 Xu Cheng 0002 Zhang Zhang Jianmin Zeng Xiaoyang Zeng A 24-bit sigma-delta ADC with configurable chopping scheme. 20190176 2019 16 IEICE Electron. Express 10 https://doi.org/10.1587/elex.16.20190176 db/journals/ieiceee/ieiceee16.html#LiCZZZ19

Xu Cheng 0002 Xiaoyang Zeng Qi Feng Analysis and improvement of ramp gain error in single-ramp single-slope ADCs for CMOS image sensors. 23-31 2016 58 Microelectron. J. https://doi.org/10.1016/j.mejo.2016.10.006 db/journals/mj/mj58.html#ChengZF16

Liang Wen Xu Cheng 0002 Shudong Tian Haibo Wen Xiaoyang Zeng Subthreshold Level Shifter With Self-Controlled Current Limiter by Detecting Output Error. 346-350 2016 63-II IEEE Trans. Circuits Syst. II Express Briefs 4 https://doi.org/10.1109/TCSII.2015.2504025 db/journals/tcas/tcasII63.html#WenCTWZ16

Liang Wen Xu Cheng 0002 Keji Zhou Shudong Tian Xiaoyang Zeng Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. 643-647 2016 63-II IEEE Trans. Circuits Syst. II Express Briefs 7 https://doi.org/10.1109/TCSII.2016.2530881 db/journals/tcas/tcasII63.html#WenCZTZ16

Yawei Guo Yue Wu Dongdong Guo Xu Cheng 0002 Zhiyi Yu Xiaoyang Zeng Non-binary digital calibration for split-capacitor DAC in SAR ADC. 20150001 2015 12 IEICE Electron. Express 4 https://doi.org/10.1587/elex.12.20150001 db/journals/ieiceee/ieiceee12.html#GuoWGCYZ15

Xiaoyang Zeng Yi Li Yuejun Zhang Shujie Tan Jun Han 0003 Xingxing Zhang Zhang Zhang Xu Cheng 0002 Zhiyi Yu Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. 1365-1369 2015 23 IEEE Trans. Very Large Scale Integr. Syst. 7 https://doi.org/10.1109/TVLSI.2014.2334693 db/journals/tvlsi/tvlsi23.html#ZengLZTHZZCHY15

Yi Li Liang Wen Yuejun Zhang Xu Cheng 0002 Jun Han 0003 Zhiyi Yu Xiaoyang Zeng An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. 20130992 2014 11 IEICE Electron. Express 3 https://doi.org/10.1587/elex.11.20130992 db/journals/ieiceee/ieiceee11.html#LiWZCHYZ14

Zhiyi Yu Ruijin Xiao Kaidi You Heng Quan Peng Ou Zheng Yu 0001 Maofei He Jiajie Zhang Yan Ying Haofan Yang 0001 Jun Han 0003 Xu Cheng 0002 Zhang Zhang Ming-e Jing Xiaoyang Zeng A 16-Core Processor With Shared-Memory and Message-Passing Communications. 1081-1094 2014 61-I IEEE Trans. Circuits Syst. I Regul. Pap. 4 https://doi.org/10.1109/TCSI.2013.2283693 db/journals/tcas/tcasI61.html#YuXYQOYHZYYHCZJZ14

Yue Wu Xu Cheng 0002 Xiaoyang Zeng A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme. 1260-1267 2013 44 Microelectron. J. 12 https://doi.org/10.1016/j.mejo.2013.08.012 db/journals/mj/mj44.html#WuCZ13

Weijing Shi Yi Li Jun Han 0003 Xu Cheng 0002 Xiaoyang Zeng An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. 1-4 2013 ASICON https://doi.org/10.1109/ASICON.2013.6811911 conf/asicon/2013 db/conf/asicon/asicon2013.html#ShiLHCZ13 Biao Wang Meng Zhang Xu Cheng 0002 Qi Feng Xiaoyang Zeng A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor. 1-4 2013 ASICON https://doi.org/10.1109/ASICON.2013.6812046 conf/asicon/2013 db/conf/asicon/asicon2013.html#WangZCFZ13 Yi Li Xu Cheng 0002 Yicheng Zhang Weijing Shi Jun Han 0003 Xiaoyang Zeng A highly energy-efficient compressed sensing encoder with robust subthreshold clockless pipeline for wireless BANs. 154-157 2013 BioCAS https://doi.org/10.1109/BioCAS.2013.6679662 conf/biocas/2013 db/conf/biocas/biocas2013.html#Li0ZS0Z13 Yue Wu Xu Cheng 0002 Xiaoyang Zeng A split-capacitor vcm-based capacitor-switching scheme for low-power SAR ADCs. 2014-2017 2013 ISCAS https://doi.org/10.1109/ISCAS.2013.6572266 conf/iscas/2013 db/conf/iscas/iscas2013.html#WuCZ13

Jun Han 0003 Xingxing Zhang Yi Li Baoyu Xiong Yuejun Zhang Zhang Zhang Zhiyi Yu Xu Cheng 0002 Xiaoyang Zeng A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. 1355-1361 2012 9 IEICE Electron. Express 16 https://doi.org/10.1587/elex.9.1355 db/journals/ieiceee/ieiceee9.html#HanZLXZZYHCZ12

Hong Chang Wenxian Lu Xu Cheng 0002 Yawei Guo Xiaoyang Zeng Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications. 465-468 2011 ASICON https://doi.org/10.1109/ASICON.2011.6157222 conf/asicon/2011 db/conf/asicon/asicon2011.html#ChangLCGZ11 Jun Ma 0005 Yawei Guo Li Li 0038 Yue Wu Xu Cheng 0002 Xiaoyang Zeng A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS. 484-487 2011 ASICON https://doi.org/10.1109/ASICON.2011.6157227 conf/asicon/2011 db/conf/asicon/asicon2011.html#MaGLWCZ11 Li Li 0038 Jun Ma 0005 Yawei Guo Xu Cheng 0002 Xiaoyang Zeng A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters. 504-507 2011 ASICON https://doi.org/10.1109/ASICON.2011.6157232 conf/asicon/2011 db/conf/asicon/asicon2011.html#LiMGCZ11 Zhang Zhang Zhiyi Yu Xu Cheng 0002 Xiaoyang Zeng A low power 1.0 GHz VCO in 65nm-CMOS LP-process. 1006-1009 2011 ASICON https://doi.org/10.1109/ASICON.2011.6157377 conf/asicon/2011 db/conf/asicon/asicon2011.html#ZhangYCZ11 Hong Chang Chao Chen Zhiyuan Chen 0002 Shaohang Chu Sijun Du Xuyang Duan Qi Feng Zhao Gao Zhengqi Gao Dongdong Guo Yawei Guo Ziyu Guo Jun Han 0003 Yuanyuan Han Maofei He Ming-e Jing Man Kay LawMan-Kay Law Jinrong Li Li Li 0038 Min Li Qiang Li Tongde Li Yan Li 0084 Yi Li Zhaojie Li Zhen Li Junrui Liang Liyu Lin Yan Liu Wenxian Lu Jun Ma 0005 Peng Ou Heng Quan Yitong Rong Weijing Shi Mehdi Baradaran TahooriMehdi B. Tahoori Chiyu Tan Shujie Tan Jun Tao 0001 Shudong Tian Biao Wang Jiawei Wang Jing Wang Jue Wang Liang Wang 0024 Song Wang Wei-Zhen Wang Weizhen Wang Haibo Wen Liang Wen Yue Wu Ruijin Xiao Guozhu Xin Baoyu Xiong Jiawei Xu 0001 Xiaoyong Xue Haofan Yang 0001 Heqing Yang Jianwei Yang Zhen Yang Zhenyu Yang Tianyu Yin Yan Ying Kaidi You Zheng Yu 0001 Zhiyi Yu Jianmin Zeng Xiaoyang Zeng Xiaoyoung Zeng Yicheng Zeng Baijie Zhang Hui Zhang Jiajie Zhang Meng Zhang Xingxing Zhang Yicheng Zhang Yong-Liang Zhang Yongliang Zhang Yuejun Zhang Zhang Zhang Yuanfu Zhao Keji Zhou Yuchao Zhou