@article{DBLP:journals/jssc/LiWLDLCHZC24,
author = {Zhen Li and
Jing Wang and
Man{-}Kay Law and
Sijun Du and
Junrui Liang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng and
Zhiyuan Chen},
title = {Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier
and Switched-PEH {DC-DC} for {MPPT}},
journal = {{IEEE} J. Solid State Circuits},
volume = {59},
number = {7},
pages = {2248--2259},
year = {2024},
url = {https://doi.org/10.1109/JSSC.2023.3341865},
doi = {10.1109/JSSC.2023.3341865},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LiWLDLCHZC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/ZhangRDYLGCZH24,
author = {Yongliang Zhang and
Yitong Rong and
Xuyang Duan and
Zhen Yang and
Qiang Li and
Ziyu Guo and
Xu Cheng and
Xiaoyang Zeng and
Jun Han},
title = {An Energy-Efficient {BNN} Accelerator With Two-Stage Value Prediction
for Sparse-Edge Gesture Recognition},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {71},
number = {1},
pages = {320--333},
year = {2024},
url = {https://doi.org/10.1109/TCSI.2023.3320175},
doi = {10.1109/TCSI.2023.3320175},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/ZhangRDYLGCZH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/HanCXHXZ24,
author = {Yuanyuan Han and
Xu Cheng and
Xiaoyong Xue and
Jun Han and
Jiawei Xu and
Xiaoyang Zeng},
title = {{SET} Tolerable {SRAM} Hardened by {DMR} Circuit With Feedback-Split-Gate
Voter and High-Speed Hierarchical Structure},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {71},
number = {3},
pages = {1416--1420},
year = {2024},
url = {https://doi.org/10.1109/TCSII.2023.3324036},
doi = {10.1109/TCSII.2023.3324036},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasII/HanCXHXZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/WangGCWLHZ24,
author = {Jiawei Wang and
Zhao Gao and
Xu Cheng and
Jue Wang and
Zhen Li and
Jun Han and
Xiaoyang Zeng},
title = {A 1.6 GS/s 42.6-dB {SNDR} Synthesis Friendly Time-Interleaved {SAR}
{ADC} Using Metastability Detection and Escape Acceleration Technique},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {71},
number = {4},
pages = {1859--1863},
year = {2024},
url = {https://doi.org/10.1109/TCSII.2023.3335987},
doi = {10.1109/TCSII.2023.3335987},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/WangGCWLHZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/Wang0G023,
author = {Song Wang and
Xu Cheng and
Ziyu Guo and
Jun Han},
title = {A foreground digital calibration algorithm for time-interleaved ADCs
with low computational complexity},
journal = {Microelectron. J.},
volume = {136},
pages = {105778},
year = {2023},
url = {https://doi.org/10.1016/j.mejo.2023.105778},
doi = {10.1016/J.MEJO.2023.105778},
timestamp = {Thu, 15 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/Wang0G023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/LiuLCHZ23,
author = {Yan Liu and
Yan Li and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {A Non-Redundant Latch With Key-Node-Upset Obstacle of Beneficial Efficiency
for Harsh Environments Applications},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {4},
pages = {1639--1648},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2023.3237706},
doi = {10.1109/TCSI.2023.3237706},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/LiuLCHZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/LiCCHZ23,
author = {Yan Li and
Chao Chen and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {{DMBF:} Design Metrics Balancing Framework for Soft-Error-Tolerant
Digital Circuits Through Bayesian Optimization},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {10},
pages = {4015--4027},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2023.3302341},
doi = {10.1109/TCSI.2023.3302341},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/LiCCHZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/ZhangWCHZ23,
author = {Baijie Zhang and
Jiawei Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {Dominant-Node Theory and Monitoring-Rescue Method for Eliminating
Undesired Operating Points in the Self-Biased Reference Generators},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {70},
number = {12},
pages = {5242--5253},
year = {2023},
url = {https://doi.org/10.1109/TCSI.2023.3318399},
doi = {10.1109/TCSI.2023.3318399},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcasI/ZhangWCHZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/LiCLDCZH23,
author = {Zhen Li and
Zhiyuan Chen and
Man{-}Kay Law and
Sijun Du and
Xu Cheng and
Xiaoyang Zeng and
Jun Han},
title = {A Self Bias-flip Piezoelectric Energy Harvester Array without External
Energy Reservoirs achieving 488{\%} Improvement with 4-Ratio Switched-PEH
{DC-DC} Converter},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2023, San Antonio,
TX, USA, April 23-26, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/CICC57935.2023.10121219},
doi = {10.1109/CICC57935.2023.10121219},
timestamp = {Sun, 21 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/LiCLDCZH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/ChuLCZ22,
author = {Shaohang Chu and
Yan Li and
Xu Cheng and
Xiaoyang Zeng},
title = {An Improved Multi-Objective Optimization Framework for Soft-Error
Immune Circuits},
booktitle = {{IEEE} Asia Pacific Conference on Circuit and Systems, {APCCAS} 2022,
Shenzhen, China, November 11-13, 2022},
pages = {481--484},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/APCCAS55924.2022.10090258},
doi = {10.1109/APCCAS55924.2022.10090258},
timestamp = {Tue, 06 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/ChuLCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhangW00Z22,
author = {Baijie Zhang and
Jue Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {An Enhanced Start-up Circuit Eliminating All Trojan States in Self-biased
Reference Generators},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {848--851},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937680},
doi = {10.1109/ISCAS48785.2022.9937680},
timestamp = {Thu, 17 Nov 2022 15:59:17 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhangW00Z22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCL00Z22,
author = {Jing Wang and
Zhiyuan Chen and
Junrui Liang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {A Cross Regulation Reduced Multi-Output and Multi-VCR Piezoelectric
Energy Harvesting System Using Shared Capacitors},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2768--2772},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937938},
doi = {10.1109/ISCAS48785.2022.9937938},
timestamp = {Wed, 05 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangCL00Z22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiWCZ22,
author = {Min Li and
Jue Wang and
Xu Cheng and
Xiaoyang Zeng},
title = {A Fully Synthesizable Dynamic Latched Comparator with Reduced Kickback
Noise},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2876--2880},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937495},
doi = {10.1109/ISCAS48785.2022.9937495},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/LiWCZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangWC0Z22,
author = {Jiawei Wang and
Jue Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {A Synthesis Friendly Dynamic Amplifier with Fuzzy-Logic Piecewise-Linear
Calibration},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2933--2937},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937746},
doi = {10.1109/ISCAS48785.2022.9937746},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangWC0Z22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/WangCHZ21,
author = {Jue Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {Synthesizable lead-lag quantization technique for digital VCO-based
{\(\Delta\)}{\(\Sigma\)} {ADC}},
journal = {Microelectron. J.},
volume = {110},
pages = {105007},
year = {2021},
url = {https://doi.org/10.1016/j.mejo.2021.105007},
doi = {10.1016/J.MEJO.2021.105007},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/WangCHZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/WangHCZ21,
author = {Weizhen Wang and
Jun Han and
Xu Cheng and
Xiaoyang Zeng},
title = {An energy-efficient crypto-extension design for {RISC-V}},
journal = {Microelectron. J.},
volume = {115},
pages = {105165},
year = {2021},
url = {https://doi.org/10.1016/j.mejo.2021.105165},
doi = {10.1016/J.MEJO.2021.105165},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/WangHCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ZhangLZWHZC21,
author = {Yong{-}Liang Zhang and
Qiang Li and
Hui Zhang and
Wei{-}Zhen Wang and
Jun Han and
Xiaoyang Zeng and
Xu Cheng},
title = {A 28 nm, 397 {\(\mu\)}W real-time dynamic gesture recognition chip
based on {RISC-V} processor},
journal = {Microelectron. J.},
volume = {116},
pages = {105219},
year = {2021},
url = {https://doi.org/10.1016/j.mejo.2021.105219},
doi = {10.1016/J.MEJO.2021.105219},
timestamp = {Fri, 01 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/ZhangLZWHZC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/HanLCWHZZ21,
author = {Yuanyuan Han and
Tongde Li and
Xu Cheng and
Liang Wang and
Jun Han and
Yuanfu Zhao and
Xiaoyang Zeng},
title = {Radiation Hardened 12T {SRAM} With Crossbar-Based Peripheral Circuit
in 28nm {CMOS} Technology},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {68},
number = {7},
pages = {2962--2975},
year = {2021},
url = {https://doi.org/10.1109/TCSI.2021.3074699},
doi = {10.1109/TCSI.2021.3074699},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/HanLCWHZZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasI/TanLCHZ21,
author = {Chiyu Tan and
Yan Li and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {General Efficient {TMR} for Combinational Circuit Hardening Against
Soft Errors and Improved Multi-Objective Optimization Framework},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {68},
number = {7},
pages = {3044--3057},
year = {2021},
url = {https://doi.org/10.1109/TCSI.2021.3076185},
doi = {10.1109/TCSI.2021.3076185},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasI/TanLCHZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiW0ZZ21,
author = {Jinrong Li and
Jue Wang and
Xu Cheng and
Yicheng Zeng and
Xiaoyang Zeng},
editor = {Fan Ye and
Ting{-}Ao Tang},
title = {A 0.9V Supply 12.5Gb/s {LVDS} Receiver in 28nm {CMOS} Process},
booktitle = {14th {IEEE} International Conference on ASIC, {ASICON} 2021, Kunming,
China, October 26-29, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASICON52560.2021.9620302},
doi = {10.1109/ASICON52560.2021.9620302},
timestamp = {Mon, 06 Dec 2021 11:20:15 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiW0ZZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhangLYCZ21,
author = {Hui Zhang and
Zhaojie Li and
Heqing Yang and
Xu Cheng and
Xiaoyang Zeng},
editor = {Fan Ye and
Ting{-}Ao Tang},
title = {A High-Efficient and Configurable Hardware Accelerator for Convolutional
Neural Network},
booktitle = {14th {IEEE} International Conference on ASIC, {ASICON} 2021, Kunming,
China, October 26-29, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASICON52560.2021.9620305},
doi = {10.1109/ASICON52560.2021.9620305},
timestamp = {Fri, 30 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ZhangLYCZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/WangYWCHZ21,
author = {Jue Wang and
Zhenyu Yang and
Jiawei Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {A Synthesizable 0.0060mm\({}^{\mbox{2}}\) VCO-Based Delta Sigma Modulator
with Digital Tri-level Feedback Scheme},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2021, Busan,
Korea, Republic of, November 7-10, 2021},
pages = {1--3},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/A-SSCC53895.2021.9634735},
doi = {10.1109/A-SSCC53895.2021.9634735},
timestamp = {Tue, 21 Dec 2021 17:54:16 +0100},
biburl = {https://dblp.org/rec/conf/asscc/WangYWCHZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/XinHYZYCZ20,
author = {Guozhu Xin and
Jun Han and
Tianyu Yin and
Yuchao Zhou and
Jianwei Yang and
Xu Cheng and
Xiaoyang Zeng},
title = {{VPQC:} {A} Domain-Specific Vector Processor for Post-Quantum Cryptography
Based on {RISC-V} Architecture},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {67-I},
number = {8},
pages = {2672--2684},
year = {2020},
url = {https://doi.org/10.1109/TCSI.2020.2983185},
doi = {10.1109/TCSI.2020.2983185},
timestamp = {Thu, 01 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/XinHYZYCZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/LiCTHZWLTZ20,
author = {Yan Li and
Xu Cheng and
Chiyu Tan and
Jun Han and
Yuanfu Zhao and
Liang Wang and
Tongde Li and
Mehdi B. Tahoori and
Xiaoyang Zeng},
title = {A Robust Hardened Latch Featuring Tolerance to Double-Node-Upset in
28nm {CMOS} for Spaceborne Application},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {67-II},
number = {9},
pages = {1619--1623},
year = {2020},
url = {https://doi.org/10.1109/TCSII.2020.3013338},
doi = {10.1109/TCSII.2020.3013338},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/LiCTHZWLTZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HanCHZ20,
author = {Yuanyuan Han and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T {SRAM} and Peripheral
Circuit in 28-nm Technology for Space Applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {4},
pages = {1089--1093},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2019.2961736},
doi = {10.1109/TVLSI.2019.2961736},
timestamp = {Thu, 09 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/HanCHZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiZGLTH0TZ20,
author = {Yan Li and
Xiaoyoung Zeng and
Zhengqi Gao and
Liyu Lin and
Jun Tao and
Jun Han and
Xu Cheng and
Mehdi B. Tahoori and
Xiaoyang Zeng},
title = {Exploring a Bayesian Optimization Framework Compatible with Digital
Standard Flow for Soft-Error-Tolerant Circuit},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218696},
doi = {10.1109/DAC18072.2020.9218696},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LiZGLTH0TZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/0002W0Z20,
author = {Xu Cheng and
Jue Wang and
Jun Han and
Xiaoyang Zeng},
title = {Design Methodology of Clock Polarity Inversion Technique for Frequency
Dividers},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180450},
doi = {10.1109/ISCAS45731.2020.9180450},
timestamp = {Mon, 18 Jan 2021 08:38:59 +0100},
biburl = {https://dblp.org/rec/conf/iscas/0002W0Z20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangCHZ20,
author = {Jue Wang and
Xu Cheng and
Jun Han and
Xiaoyang Zeng},
title = {A Synthesis Friendly VCO-Based Delta-Sigma {ADC} with Process Variation
Tolerance},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180939},
doi = {10.1109/ISCAS45731.2020.9180939},
timestamp = {Tue, 19 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/WangCHZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/LiCZZZ19,
author = {Li Li and
Xu Cheng and
Zhang Zhang and
Jianmin Zeng and
Xiaoyang Zeng},
title = {A 24-bit sigma-delta {ADC} with configurable chopping scheme},
journal = {{IEICE} Electron. Express},
volume = {16},
number = {10},
pages = {20190176},
year = {2019},
url = {https://doi.org/10.1587/elex.16.20190176},
doi = {10.1587/ELEX.16.20190176},
timestamp = {Fri, 12 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/LiCZZZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ChengZF16,
author = {Xu Cheng and
Xiaoyang Zeng and
Qi Feng},
title = {Analysis and improvement of ramp gain error in single-ramp single-slope
ADCs for {CMOS} image sensors},
journal = {Microelectron. J.},
volume = {58},
pages = {23--31},
year = {2016},
url = {https://doi.org/10.1016/j.mejo.2016.10.006},
doi = {10.1016/J.MEJO.2016.10.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/ChengZF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Liang Wen and
Xu Cheng and
Shudong Tian and
Haibo Wen and
Xiaoyang Zeng},
title = {Subthreshold Level Shifter With Self-Controlled Current Limiter by
Detecting Output Error},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {4},
pages = {346--350},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2015.2504025},
doi = {10.1109/TCSII.2015.2504025},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WenCTWZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Liang Wen and
Xu Cheng and
Keji Zhou and
Shudong Tian and
Xiaoyang Zeng},
title = {Bit-Interleaving-Enabled 8T {SRAM} With Shared Data-Aware Write and
Reference-Based Sense Amplifier},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {63-II},
number = {7},
pages = {643--647},
year = {2016},
url = {https://doi.org/10.1109/TCSII.2016.2530881},
doi = {10.1109/TCSII.2016.2530881},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/WenCZTZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/GuoWGCYZ15,
author = {Yawei Guo and
Yue Wu and
Dongdong Guo and
Xu Cheng and
Zhiyi Yu and
Xiaoyang Zeng},
title = {Non-binary digital calibration for split-capacitor {DAC} in {SAR}
{ADC}},
journal = {{IEICE} Electron. Express},
volume = {12},
number = {4},
pages = {20150001},
year = {2015},
url = {https://doi.org/10.1587/elex.12.20150001},
doi = {10.1587/ELEX.12.20150001},
timestamp = {Fri, 12 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/GuoWGCYZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Xiaoyang Zeng and
Yi Li and
Yuejun Zhang and
Shujie Tan and
Jun Han and
Xingxing Zhang and
Zhang Zhang and
Xu Cheng and
Zhiyi Yu},
title = {Design and Analysis of Highly Energy/Area-Efficient Multiported Register
Files With Read Word-Line Sharing Strategy in 65-nm {CMOS} Process},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {7},
pages = {1365--1369},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2334693},
doi = {10.1109/TVLSI.2014.2334693},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZengLZTHZZCHY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/LiWZCHYZ14,
author = {Yi Li and
Liang Wen and
Yuejun Zhang and
Xu Cheng and
Jun Han and
Zhiyi Yu and
Xiaoyang Zeng},
title = {An area-efficient dual replica-bitline delay technique for process-variation-tolerant
low voltage {SRAM} sense amplifier timing},
journal = {{IEICE} Electron. Express},
volume = {11},
number = {3},
pages = {20130992},
year = {2014},
url = {https://doi.org/10.1587/elex.11.20130992},
doi = {10.1587/ELEX.11.20130992},
timestamp = {Fri, 12 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/LiWZCHYZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Zhiyi Yu and
Ruijin Xiao and
Kaidi You and
Heng Quan and
Peng Ou and
Zheng Yu and
Maofei He and
Jiajie Zhang and
Yan Ying and
Haofan Yang and
Jun Han and
Xu Cheng and
Zhang Zhang and
Ming{-}e Jing and
Xiaoyang Zeng},
title = {A 16-Core Processor With Shared-Memory and Message-Passing Communications},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {61-I},
number = {4},
pages = {1081--1094},
year = {2014},
url = {https://doi.org/10.1109/TCSI.2013.2283693},
doi = {10.1109/TCSI.2013.2283693},
timestamp = {Mon, 17 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/YuXYQOYHZYYHCZJZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/WuCZ13,
author = {Yue Wu and
Xu Cheng and
Xiaoyang Zeng},
title = {A 960 {\(\mu\)}W 10-bit 70-MS/s {SAR} {ADC} with an energy-efficient
capacitor-switching scheme},
journal = {Microelectron. J.},
volume = {44},
number = {12},
pages = {1260--1267},
year = {2013},
url = {https://doi.org/10.1016/j.mejo.2013.08.012},
doi = {10.1016/J.MEJO.2013.08.012},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/WuCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ShiLHCZ13,
author = {Weijing Shi and
Yi Li and
Jun Han and
Xu Cheng and
Xiaoyang Zeng},
title = {An extensible and real-time compressive sensing reconstruction hardware
for WBANs using {OMP}},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6811911},
doi = {10.1109/ASICON.2013.6811911},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ShiLHCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/WangZCFZ13,
author = {Biao Wang and
Meng Zhang and
Xu Cheng and
Qi Feng and
Xiaoyang Zeng},
title = {A 1.8-V 14-bit inverter-based incremental {\(\Sigma\)}{\(\Delta\)}
{ADC} for {CMOS} image sensor},
booktitle = {{IEEE} 10th International Conference on ASIC, {ASICON} 2013, Shenzhen,
China, October 28-31, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASICON.2013.6812046},
doi = {10.1109/ASICON.2013.6812046},
timestamp = {Wed, 17 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/WangZCFZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biocas/Li0ZS0Z13,
author = {Yi Li and
Xu Cheng and
Yicheng Zhang and
Weijing Shi and
Jun Han and
Xiaoyang Zeng},
title = {A highly energy-efficient compressed sensing encoder with robust subthreshold
clockless pipeline for wireless BANs},
booktitle = {2013 {IEEE} Biomedical Circuits and Systems Conference (BioCAS), Rotterdam,
The Netherlands, October 31 - Nov. 2, 2013},
pages = {154--157},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/BioCAS.2013.6679662},
doi = {10.1109/BIOCAS.2013.6679662},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/biocas/Li0ZS0Z13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WuCZ13,
author = {Yue Wu and
Xu Cheng and
Xiaoyang Zeng},
title = {A split-capacitor vcm-based capacitor-switching scheme for low-power
{SAR} ADCs},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {2014--2017},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572266},
doi = {10.1109/ISCAS.2013.6572266},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WuCZ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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author = {Jun Han and
Xingxing Zhang and
Yi Li and
Baoyu Xiong and
Yuejun Zhang and
Zhang Zhang and
Zhiyi Yu and
Xu Cheng and
Xiaoyang Zeng},
title = {A 64{\texttimes}32bit 4-read 2-write low power and area efficient
register file in 65nm {CMOS}},
journal = {{IEICE} Electron. Express},
volume = {9},
number = {16},
pages = {1355--1361},
year = {2012},
url = {https://doi.org/10.1587/elex.9.1355},
doi = {10.1587/ELEX.9.1355},
timestamp = {Fri, 12 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/HanZLXZZYHCZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ChangLCGZ11,
author = {Hong Chang and
Wenxian Lu and
Xu Cheng and
Yawei Guo and
Xiaoyang Zeng},
title = {Modeling of a double-sampling switched-capacitor bandpass delta-sigma
modulator for multi-standard applications},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {465--468},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157222},
doi = {10.1109/ASICON.2011.6157222},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/asicon/ChangLCGZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/MaGLWCZ11,
author = {Jun Ma and
Yawei Guo and
Li Li and
Yue Wu and
Xu Cheng and
Xiaoyang Zeng},
title = {A low power 10-bit 100-MS/s {SAR} {ADC} in 65nm {CMOS}},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {484--487},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157227},
doi = {10.1109/ASICON.2011.6157227},
timestamp = {Wed, 17 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/MaGLWCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/LiMGCZ11,
author = {Li Li and
Jun Ma and
Yawei Guo and
Xu Cheng and
Xiaoyang Zeng},
title = {A multi-mode 1-V DAC+filter in 65-nm {CMOS} for reconfigurable (GSM,
{TD-SCDMA} and {WCDMA)} transmitters},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {504--507},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157232},
doi = {10.1109/ASICON.2011.6157232},
timestamp = {Wed, 17 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/LiMGCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ZhangYCZ11,
author = {Zhang Zhang and
Zhiyi Yu and
Xu Cheng and
Xiaoyang Zeng},
title = {A low power 1.0 GHz {VCO} in 65nm-CMOS LP-process},
booktitle = {2011 {IEEE} 9th International Conference on ASIC, {ASICON} 2011, Xiamen,
China, October 25-28, 2011},
pages = {1006--1009},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASICON.2011.6157377},
doi = {10.1109/ASICON.2011.6157377},
timestamp = {Wed, 17 Jan 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ZhangYCZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
