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2020 – today
- 2024
[c28]Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang:
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. VLSI Technology and Circuits 2024: 1-2- [c27]Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu:
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. VLSI Technology and Circuits 2024: 1-2 - 2022
- [c26]Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu:
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. VLSI Technology and Circuits 2022: 262-263 - [c25]Zhong-Jie Hong, Demin Liu, Shu-Ting Hsieh, Han-Wen Hu, Ming-Wei Weng, Chih-I Cho, Jui-Han Liu, Kuan-Neng Chen:
Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and Packaging. VLSI Technology and Circuits 2022: 387-388
2010 – 2019
- 2019
- [c24]Po-Chih Chen, Demin Liu, Kuan-Neng Chen:
Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °C. 3DIC 2019: 1-4 - [c23]Chia-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, Hiroyuki Ito, Young-Suk Kim, Kuan-Neng Chen, Takayuki Ohba:
Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias. 3DIC 2019: 1-4 - [c22]Demin Liu, Po-Chih Chen, Yi-Chieh Tsai, Kuan-Neng Chen:
Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer. 3DIC 2019: 1-4 - [c21]Yi-Chieh Tsai, Chia-Hsuan Lee, Kuan-Neng Chen:
Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology. 3DIC 2019: 1-4 - 2017
- [j9]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. 11(5): 1013-1025 (2017) - [c20]Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen
, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS 2017: 1-4 - 2016
- [c19]Hao-Wen Liang, Hsiu-Chi Chen, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen:
The influence of device morphology on wafer-level bonding with polymer-coated layer. 3DIC 2016: 1-4 - [c18]Yu-Tao Yang, Yu-Chen Hu, Kuan-Neng Chen:
Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration. 3DIC 2016: 1-4 - [c17]Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou:
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS 2016: 1302-1305 - 2015
- [c16]Chuan-An Cheng, Ryuichi Sugie, Tomoyuki Uchida, Kou-Hua Chen, Chi-Tsung Chiu, Kuan-Neng Chen:
Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration. 3DIC 2015: TS8.12.1-TS8.12.4 - [c15]Tsung-Yen Tsai, Chien-Hung Lin, Chia-Lin Lee, Shan-Chun Yang, Kuan-Neng Chen:
An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration. 3DIC 2015: TS8.8.1-TS8.8.5 - 2014
- [j8]Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong:
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. 8(6): 810-823 (2014) - [c14]Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS 2014: 1841-1844 - [c13]Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-Lung Lin, Ho-Ming Tong:
18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC 2014: 320-321 - [c12]Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT 2014: 1-4 - 2013
- [j7]Cheng-Ta Ko, Kuan-Neng Chen:
Reliability of key technologies in 3D integration. Microelectron. Reliab. 53(1): 7-16 (2013) - [c11]Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen:
Low temperature (<180 °C) bonding for 3D integration. 3DIC 2013: 1-5 - [c10]Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang:
Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS 2013: 238-241 - [c9]Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS 2013: 133-136 - [c8]Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong:
Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC 2013: 102-103 - 2012
- [j6]Cheng-Ta Ko, Kuan-Neng Chen:
Low temperature bonding technology for 3D integration. Microelectron. Reliab. 52(2): 302-311 (2012) - [j5]Ya-Sheng Tang, Yao-Jen Chang, Kuan-Neng Chen:
Wafer-level Cu-Cu bonding technology. Microelectron. Reliab. 52(2): 312-320 (2012) - [j4]S. L. Lin, W. C. Huang, C. T. Ko, Kuan-Neng Chen:
BCB-to-oxide bonding technology for 3D integration. Microelectron. Reliab. 52(2): 352-355 (2012) - [c7]Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang:
On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC 2012: 370-375 - 2011
- [j3]Kuan-Neng Chen, Chuan Seng Tan:
Integration schemes and enabling technologies for three-dimensional integrated circuits. IET Comput. Digit. Tech. 5(3): 160-168 (2011) - [c6]Kuan-Neng Chen, Z. Xu, Fei Liu, Cheng-Ta Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Zhi-Cheng Hsiao, N. Klymko, Hsin-Chia Fu, Y. H. Chen, Jian-Qiang Lu, Wei-Chung Lo:
Cu-based bonding technology for 3D integration applications. 3DIC 2011: 1-4 - [c5]Cheng-Ta Ko, Zhi-Cheng Hsiao, Y. J. Chang, Peng-Shu Chen, J. H. Huang, Hsin-Chia Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, Wei-Chung Lo, Kuan-Neng Chen:
Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies. 3DIC 2011: 1-4 - 2010
- [j2]Cheng-Ta Ko, Kuan-Neng Chen:
Wafer-level bonding/stacking technology for 3D integration. Microelectron. Reliab. 50(4): 481-488 (2010) - [c4]Cheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo, Chuan-An Cheng, Wen-Chun Huang, Zhi-Cheng Hsiao, Huan-Chun Fu, Yu-Hua Chen:
Wafer-level 3D integration using hybrid bonding. 3DIC 2010: 1-4 - [c3]Zheng Xu, Adam Beece, Dingyou Zhang, Qianwen Chen, Kuan-Neng Chen, Kenneth Rose, Jian-Qiang Lu:
Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network. 3DIC 2010: 1-8
2000 – 2009
- 2008
- [j1]Steven J. Koester, Albert M. Young, Roy R. Yu, Sampath Purushothaman, Kuan-Neng Chen, Douglas C. La Tulipe Jr., Narender Rana, Leathen Shi, Matthew R. Wordeman, Edmund J. Sprogis:
Wafer-level 3D integration technology. IBM J. Res. Dev. 52(6): 583-597 (2008) - 2005
- [b1]Kuan-Neng Chen:
Copper wafer bonding in three-dimensional integration. Massachusetts Institute of Technology, Cambridge, MA, USA, 2005 - 2004
- [c2]Shamik Das, Andy Fan, Kuan-Neng Chen, Chuan Seng Tan, Nisha Checka, Rafael Reif:
Technology, performance, and computer-aided design of three-dimensional integrated circuits. ISPD 2004: 108-115 - 2002
- [c1]Rafael Reif, Andy Fan, Kuan-Neng Chen, Shamik Das:
Fabrication Technologies for Three-Dimensional Integrated Circuits (invited). ISQED 2002: 33-37
Coauthor Index
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