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Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - JOUR ID - DBLP:journals/chinaf/ZhaoYLCYWJWZZ23 AU - Zhao, Yinglin AU - Yang, Jianlei AU - Li, Bing AU - Cheng, Xingzhou AU - Ye, Xucheng AU - Wang, Xueyan AU - Jia, Xiaotao AU - Wang, Zhaohao AU - Zhang, Youguang AU - Zhao, Weisheng TI - NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. JO - Sci. China Inf. Sci. VL - 66 IS - 4 PY - 2023/04/ DO - 10.1007/S11432-021-3472-9 UR - https://doi.org/10.1007/s11432-021-3472-9 ER - TY - JOUR ID - DBLP:journals/phycomm/DaiZYKSL23 AU - Dai, Mingjun AU - Zhao, Yinglin AU - Yuan, Jialong AU - Kianoush, Sanaz AU - Savazzi, Stefano AU - Li, Bingchun TI - Federated learning based on asynchronous and adjusted client training. JO - Phys. Commun. VL - 61 SP - 102164 PY - 2023/12/ DO - 10.1016/J.PHYCOM.2023.102164 UR - https://doi.org/10.1016/j.phycom.2023.102164 ER - TY - JOUR ID - DBLP:journals/tc/WangYZJYCQZ22 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Jia, Xiaotao AU - Yin, Rong AU - Chen, Xuhang AU - Qu, Gang AU - Zhao, Weisheng TI - Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. JO - IEEE Trans. Computers VL - 71 IS - 10 SP - 2462 EP - 2472 PY - 2022// DO - 10.1109/TC.2021.3131049 UR - https://doi.org/10.1109/TC.2021.3131049 UR - https://www.wikidata.org/entity/Q114085226 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2204-09989 AU - Zhao, Yinglin AU - Yang, Jianlei AU - Li, Bing AU - Cheng, Xingzhou AU - Ye, Xucheng AU - Wang, Xueyan AU - Jia, Xiaotao AU - Wang, Zhaohao AU - Zhang, Youguang AU - Zhao, Weisheng TI - NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. JO - CoRR VL - abs/2204.09989 PY - 2022// DO - 10.48550/ARXIV.2204.09989 UR - https://doi.org/10.48550/arXiv.2204.09989 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2112-00471 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Jia, Xiaotao AU - Yin, Rong AU - Chen, Xuhang AU - Qu, Gang AU - Zhao, Weisheng TI - Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. JO - CoRR VL - abs/2112.00471 PY - 2021// UR - https://arxiv.org/abs/2112.00471 ER - TY - JOUR ID - DBLP:journals/jetc/WangYZJQZ20 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Jia, Xiaotao AU - Qu, Gang AU - Zhao, Weisheng TI - Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. JO - ACM J. Emerg. Technol. Comput. Syst. VL - 16 IS - 4 SP - 37:1 EP - 37:18 PY - 2020// DO - 10.1145/3397513 UR - https://doi.org/10.1145/3397513 UR - https://www.wikidata.org/entity/Q113434136 ER - TY - CPAPER ID - DBLP:conf/dac/WangYZQLCJCQZ20 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Qi, Yingjie AU - Liu, Meichen AU - Cheng, Xingzhou AU - Jia, Xiaotao AU - Chen, Xiaoming AU - Qu, Gang AU - Zhao, Weisheng TI - TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. BT - 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020 SP - 1 EP - 6 PY - 2020// DO - 10.1109/DAC18072.2020.9218660 UR - https://doi.org/10.1109/DAC18072.2020.9218660 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2006-01425 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Jia, Xiaotao AU - Qu, Gang AU - Zhao, Weisheng TI - Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques. JO - CoRR VL - abs/2006.01425 PY - 2020// UR - https://arxiv.org/abs/2006.01425 ER - TY - Informal or Other Publication ID - DBLP:journals/corr/abs-2007-10702 AU - Wang, Xueyan AU - Yang, Jianlei AU - Zhao, Yinglin AU - Qi, Yingjie AU - Liu, Meichen AU - Cheng, Xingzhou AU - Jia, Xiaotao AU - Chen, Xiaoming AU - Qu, Gang AU - Zhao, Weisheng TI - TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. JO - CoRR VL - abs/2007.10702 PY - 2020// UR - https://arxiv.org/abs/2007.10702 ER - TY - JOUR ID - DBLP:journals/tc/ZhaoOKYZWZ19 AU - Zhao, Yinglin AU - Ouyang, Peng AU - Kang, Wang AU - Yin, Shouyi AU - Zhang, Youguang AU - Wei, Shaojun AU - Zhao, Weisheng TI - An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. JO - IEEE Trans. Computers VL - 68 IS - 4 SP - 617 EP - 623 PY - 2019// DO - 10.1109/TC.2018.2879502 UR - https://doi.org/10.1109/TC.2018.2879502 ER - TY - CPAPER ID - DBLP:conf/glvlsi/PanOZYZWZ19 AU - Pan, Yu AU - Ouyang, Peng AU - Zhao, Yinglin AU - Yin, Shouyi AU - Zhang, Youguang AU - Wei, Shaojun AU - Zhao, Weisheng TI - A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network. BT - Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019 SP - 271 EP - 274 PY - 2019// DO - 10.1145/3299874.3318015 UR - https://doi.org/10.1145/3299874.3318015 ER - TY - CPAPER ID - DBLP:conf/isvlsi/ZhaoYJWWKZZ19 AU - Zhao, Yinglin AU - Yang, Jianlei AU - Jia, Xiaotao AU - Wang, Xueyan AU - Wang, Zhaohao AU - Kang, Wang AU - Zhang, Youguang AU - Zhao, Weisheng TI - Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. BT - 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019 SP - 203 EP - 206 PY - 2019// DO - 10.1109/ISVLSI.2019.00045 UR - https://doi.org/10.1109/ISVLSI.2019.00045 ER - TY - JOUR ID - DBLP:journals/jcst/ZhaoYZTC18 AU - Zhao, Yinglin AU - Yang, Jianlei AU - Zhao, Weisheng AU - Todri-Sanial, Aida AU - Cheng, Yuanqing TI - Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. JO - J. Comput. Sci. Technol. VL - 33 IS - 5 SP - 966 EP - 983 PY - 2018// DO - 10.1007/S11390-018-1868-6 UR - https://doi.org/10.1007/s11390-018-1868-6 ER -