dblp: Haeyoon Cho
https://dblp.org/pid/224/5725-2.html
dblp person page RSS feedMon, 07 Oct 2024 21:17:39 +0200en-USdaily1released under the CC0 1.0 licensedblp@dagstuhl.de (dblp team)dblp@dagstuhl.de (dblp team)Computers/Computer_Science/Publications/Bibliographieshttp://www.rssboard.org/rss-specificationhttps://dblp.org/img/logo.144x51.pngdblp: Haeyoon Chohttps://dblp.org/pid/224/5725-2.html14451Scalability Limitations of Processing-in-Memory using Real System Evaluations.https://doi.org/10.1145/3639046Gilbert Jonatan, Haeyoon Cho, Hyojun Son, Xiangyu Wu, Neal Livesay, Evelio Mora, Kaustubh Shivdikar, José L. Abellán, Ajay Joshi, David R. Kaeli, John Kim: Scalability Limitations of Processing-in-Memory using Real System Evaluations.Proc. ACM Meas. Anal. Comput. Syst.8(1): 5:1-5:28 (2024)]]>https://dblp.org/rec/journals/pomacs/Jonatan0SWLMSAJ24Mon, 01 Jan 2024 00:00:00 +0100Scalability Limitations of Processing-in-Memory using Real System Evaluations.https://doi.org/10.1145/3652963.3655079Gilbert Jonatan, Haeyoon Cho, Hyojun Son, Xiangyu Wu, Neal Livesay, Evelio Mora, Kaustubh Shivdikar, José L. Abellán, Ajay Joshi, David R. Kaeli, John Kim: Scalability Limitations of Processing-in-Memory using Real System Evaluations.SIGMETRICS/Performance (Abstracts)2024: 63-64]]>https://dblp.org/rec/conf/sigmetrics/Jonatan0SWLMSAJ24Mon, 01 Jan 2024 00:00:00 +0100CT-Cache: Compressed Tag-Driven Cache Architecture.https://doi.org/10.1109/ISVLSI.2018.00027Haeyoon Cho, Joonho Kong, Arslan Munir, Naresh Kumar Giri: CT-Cache: Compressed Tag-Driven Cache Architecture.ISVLSI2018: 94-99]]>https://dblp.org/rec/conf/isvlsi/ChoKMG18Mon, 01 Jan 2018 00:00:00 +0100