iBet uBet web content aggregator. Adding the entire web to your favor.

Link to original content: https://dblp.org/pid/222/1926.rss

dblp: Philippos Papaphilippou https://dblp.org/pid/222/1926.html dblp person page RSS feed Mon, 05 Aug 2024 20:20:09 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Philippos Papaphilippouhttps://dblp.org/pid/222/1926.html14451 Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers.https://doi.org/10.1109/TC.2024.3365954Philippos Papaphilippou

, Thiem Van Chu

:
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers. IEEE Trans. Computers 73(5): 1414-1426 (2024)]]>https://dblp.org/rec/journals/tc/PapaphilippouC24Wed, 01 May 2024 01:00:00 +0200 Efficient Adaptable Streaming Aggregation Engine.https://doi.org/10.48550/arXiv.2405.18168Philippos Papaphilippou

, Wayne Luk:
Efficient Adaptable Streaming Aggregation Engine. CoRR abs/2405.18168 (2024)]]>https://dblp.org/rec/journals/corr/abs-2405-18168Mon, 01 Jan 2024 00:00:00 +0100 Revisiting 3D Cartesian Scatterplots with a Novel Plotting Framework and a Survey.https://doi.org/10.48550/arXiv.2406.06146Philippos Papaphilippou

:
Revisiting 3D Cartesian Scatterplots with a Novel Plotting Framework and a Survey. CoRR abs/2406.06146 (2024)]]>https://dblp.org/rec/journals/corr/abs-2406-06146Mon, 01 Jan 2024 00:00:00 +0100 Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer.https://doi.org/10.1109/TPDS.2023.3244589Philippos Papaphilippou

, Kentaro Sano

, Boma Anantasatya Adhi

, Wayne Luk:
Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. 34(5): 1621-1634 (2023)]]>https://dblp.org/rec/journals/tpds/PapaphilippouSAL23Mon, 01 May 2023 01:00:00 +0200 Efficiently Removing Sparsity for High-Throughput Stream Processing.https://doi.org/10.1109/ICFPT59805.2023.00033Philippos Papaphilippou

, Zhiqiang Que, Wayne Luk:
Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT 2023: 244-249]]>https://dblp.org/rec/conf/fpt/PapaphilippouQL23Sun, 01 Jan 2023 00:00:00 +0100 Efficient deadlock avoidance in 2D mesh NoCs that use OQ or VOQ routers.https://doi.org/10.48550/arXiv.2303.10526Philippos Papaphilippou

:
Efficient deadlock avoidance in 2D mesh NoCs that use OQ or VOQ routers. CoRR abs/2303.10526 (2023)]]>https://dblp.org/rec/journals/corr/abs-2303-10526Sun, 01 Jan 2023 00:00:00 +0100 FLiMS: A Fast Lightweight 2-Way Merger for Sorting.https://doi.org/10.1109/TC.2022.3146509Philippos Papaphilippou

, Wayne Luk, Chris Brooks:
FLiMS: A Fast Lightweight 2-Way Merger for Sorting. IEEE Trans. Computers 71(12): 3215-3226 (2022)]]>https://dblp.org/rec/journals/tc/PapaphilippouLB22Sat, 01 Jan 2022 00:00:00 +0100 Hipernetch: High-Performance FPGA Network Switch.https://doi.org/10.1145/3477054Philippos Papaphilippou

, Jiuxi Meng, Nadeen Gebara, Wayne Luk:
Hipernetch: High-Performance FPGA Network Switch. ACM Trans. Reconfigurable Technol. Syst. 15(1): 3:1-3:31 (2022)]]>https://dblp.org/rec/journals/trets/PapaphilippouMG22Sat, 01 Jan 2022 00:00:00 +0100 FPGA-Extended General Purpose Computer Architecture.https://doi.org/10.1007/978-3-031-19983-7_7Philippos Papaphilippou

, Myrtle Shah

:
FPGA-Extended General Purpose Computer Architecture. ARC 2022: 87-102]]>https://dblp.org/rec/conf/arc/PapaphilippouS22Sat, 01 Jan 2022 00:00:00 +0100 FPGA-extended Modified Harvard Architecture.https://doi.org/10.48550/arXiv.2203.10359Philippos Papaphilippou

:
FPGA-extended Modified Harvard Architecture. CoRR abs/2203.10359 (2022)]]>https://dblp.org/rec/journals/corr/abs-2203-10359Sat, 01 Jan 2022 00:00:00 +0100 Demonstrating custom SIMD instruction development for a RISC-V softcore.https://doi.org/10.1109/FPL53798.2021.00030Philippos Papaphilippou

, Paul H. J. Kelly, Wayne Luk:
Demonstrating custom SIMD instruction development for a RISC-V softcore. FPL 2021: 139]]>https://dblp.org/rec/conf/fpl/PapaphilippouKL21Fri, 01 Jan 2021 00:00:00 +0100 Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions.https://doi.org/10.1109/FPL53798.2021.00082Philippos Papaphilippou

, Paul H. J. Kelly, Wayne Luk:
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. FPL 2021: 391-397]]>https://dblp.org/rec/conf/fpl/PapaphilippouKL21aFri, 01 Jan 2021 00:00:00 +0100 Efficient Queue-Balancing Switch for FPGAs.https://doi.org/10.1109/ICFPT52863.2021.9609867Philippos Papaphilippou

, Kentaro Sano, Boma A. Adhi

, Wayne Luk:
Efficient Queue-Balancing Switch for FPGAs. FPT 2021: 1-5]]>https://dblp.org/rec/conf/fpt/PapaphilippouSA21Fri, 01 Jan 2021 00:00:00 +0100 Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions.https://arxiv.org/abs/2106.07456Philippos Papaphilippou

, Paul H. J. Kelly, Wayne Luk:
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. CoRR abs/2106.07456 (2021)]]>https://dblp.org/rec/journals/corr/abs-2106-07456Fri, 01 Jan 2021 00:00:00 +0100 FLiMS: a Fast Lightweight 2-way Merge Sorter.https://arxiv.org/abs/2112.05607Philippos Papaphilippou, Wayne Luk, Chris Brooks:
FLiMS: a Fast Lightweight 2-way Merge Sorter. CoRR abs/2112.05607 (2021)]]>https://dblp.org/rec/journals/corr/abs-2112-05607Fri, 01 Jan 2021 00:00:00 +0100 High-Performance FPGA Network Switch Architecture.https://doi.org/10.1145/3373087.3375299Philippos Papaphilippou

, Jiuxi Meng, Wayne Luk:
High-Performance FPGA Network Switch Architecture. FPGA 2020: 76-85]]>https://dblp.org/rec/conf/fpga/PapaphilippouML20Wed, 01 Jan 2020 00:00:00 +0100 An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics.https://doi.org/10.1109/FPL50879.2020.00021Philippos Papaphilippou

, Chris Brooks, Wayne Luk:
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. FPL 2020: 65-72]]>https://dblp.org/rec/conf/fpl/PapaphilippouBL20Wed, 01 Jan 2020 00:00:00 +0100 Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice.https://doi.org/10.1016/j.cpc.2018.10.008Stefan Krieg

, Thomas Luu

, Johann Ostmeyer

, Philippos Papaphilippou

, Carsten Urbach

:
Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice. Comput. Phys. Commun. 236: 15-25 (2019)]]>https://dblp.org/rec/journals/cphysics/KriegLOPU19Tue, 01 Jan 2019 00:00:00 +0100 Accelerating the Merge Phase of Sort-Merge Join.https://doi.org/10.1109/FPL.2019.00025Philippos Papaphilippou

, Holger Pirk, Wayne Luk:
Accelerating the Merge Phase of Sort-Merge Join. FPL 2019: 100-105]]>https://dblp.org/rec/conf/fpl/PapaphilippouPL19Tue, 01 Jan 2019 00:00:00 +0100 Pangloss: a novel Markov chain prefetcher.http://arxiv.org/abs/1906.00877Philippos Papaphilippou

, Paul H. J. Kelly, Wayne Luk:
Pangloss: a novel Markov chain prefetcher. CoRR abs/1906.00877 (2019)]]>https://dblp.org/rec/journals/corr/abs-1906-00877Tue, 01 Jan 2019 00:00:00 +0100 Accelerating Database Systems Using FPGAs: A Survey.https://doi.org/10.1109/FPL.2018.00030Philippos Papaphilippou

, Wayne Luk:
Accelerating Database Systems Using FPGAs: A Survey. FPL 2018: 125-130]]>https://dblp.org/rec/conf/fpl/PapaphilippouL18Mon, 01 Jan 2018 00:00:00 +0100 FLiMS: Fast Lightweight Merge Sorter.https://doi.org/10.1109/FPT.2018.00022Philippos Papaphilippou

, Chris Brooks, Wayne Luk:
FLiMS: Fast Lightweight Merge Sorter. FPT 2018: 78-85]]>https://dblp.org/rec/conf/fpt/PapaphilippouBL18Mon, 01 Jan 2018 00:00:00 +0100 Performance tuning for deep learning on a many-core processor (master thesis).http://arxiv.org/abs/1806.01105Philippos Papaphilippou:
Performance tuning for deep learning on a many-core processor (master thesis). CoRR abs/1806.01105 (2018)]]>https://dblp.org/rec/journals/corr/abs-1806-01105Mon, 01 Jan 2018 00:00:00 +0100