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ORCIDPhilippos Papaphilippou
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2020 – today
- 2024
[j5]Philippos Papaphilippou
, Thiem Van Chu:
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers. IEEE Trans. Computers 73(5): 1414-1426 (2024)- [i8]Philippos Papaphilippou, Wayne Luk:
Efficient Adaptable Streaming Aggregation Engine. CoRR abs/2405.18168 (2024) - [i7]Philippos Papaphilippou:
Revisiting 3D Cartesian Scatterplots with a Novel Plotting Framework and a Survey. CoRR abs/2406.06146 (2024) - 2023
- [j4]Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk:
Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. 34(5): 1621-1634 (2023) - [c10]Philippos Papaphilippou, Zhiqiang Que, Wayne Luk:
Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT 2023: 244-249 - [i6]Philippos Papaphilippou:
Efficient deadlock avoidance in 2D mesh NoCs that use OQ or VOQ routers. CoRR abs/2303.10526 (2023) - 2022
- [j3]Philippos Papaphilippou, Wayne Luk, Chris Brooks:
FLiMS: A Fast Lightweight 2-Way Merger for Sorting. IEEE Trans. Computers 71(12): 3215-3226 (2022) - [j2]Philippos Papaphilippou, Jiuxi Meng, Nadeen Gebara, Wayne Luk:
Hipernetch: High-Performance FPGA Network Switch. ACM Trans. Reconfigurable Technol. Syst. 15(1): 3:1-3:31 (2022) - [c9]Philippos Papaphilippou, Myrtle Shah:
FPGA-Extended General Purpose Computer Architecture. ARC 2022: 87-102 - [i5]Philippos Papaphilippou:
FPGA-extended Modified Harvard Architecture. CoRR abs/2203.10359 (2022) - 2021
- [c8]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Demonstrating custom SIMD instruction development for a RISC-V softcore. FPL 2021: 139 - [c7]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. FPL 2021: 391-397 - [c6]Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk:
Efficient Queue-Balancing Switch for FPGAs. FPT 2021: 1-5 - [i4]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. CoRR abs/2106.07456 (2021) - [i3]Philippos Papaphilippou, Wayne Luk, Chris Brooks:
FLiMS: a Fast Lightweight 2-way Merge Sorter. CoRR abs/2112.05607 (2021) - 2020
- [c5]Philippos Papaphilippou, Jiuxi Meng, Wayne Luk:
High-Performance FPGA Network Switch Architecture. FPGA 2020: 76-85 - [c4]Philippos Papaphilippou, Chris Brooks, Wayne Luk:
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. FPL 2020: 65-72
2010 – 2019
- 2019
- [j1]Stefan Krieg, Thomas Luu, Johann Ostmeyer, Philippos Papaphilippou, Carsten Urbach:
Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice. Comput. Phys. Commun. 236: 15-25 (2019) - [c3]Philippos Papaphilippou, Holger Pirk, Wayne Luk:
Accelerating the Merge Phase of Sort-Merge Join. FPL 2019: 100-105 - [i2]Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk:
Pangloss: a novel Markov chain prefetcher. CoRR abs/1906.00877 (2019) - 2018
- [c2]Philippos Papaphilippou, Wayne Luk:
Accelerating Database Systems Using FPGAs: A Survey. FPL 2018: 125-130 - [c1]Philippos Papaphilippou, Chris Brooks, Wayne Luk:
FLiMS: Fast Lightweight Merge Sorter. FPT 2018: 78-85 - [i1]Philippos Papaphilippou:
Performance tuning for deep learning on a many-core processor (master thesis). CoRR abs/1806.01105 (2018)
Coauthor Index
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last updated on 2024-08-05 20:20 CEST by the dblp team
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