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ORCIDJan Mulder
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2010 – 2019
- 2017
[c12]Jan Mulder, Paul Ferguson, Un-Ku Moon:
Session 16 overview: Gigahertz data converters. ISSCC 2017: 274-275- 2016
- [j12]Edgar Sánchez-Sinencio, Jan Mulder, Antonio Liscidini
, Eric A. M. Klumperink, Elad Alon:
Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 51(12): 2803-2807 (2016) - 2015
- [c11]Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult:
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. ISSCC 2015: 1-3 - 2014
- [j11]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult:
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 2835-2845 (2014) - [c10]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC 2014: 1-8 - [c9]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC 2014: 146-147 - [c8]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult:
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. ISSCC 2014: 200-201 - 2011
- [j10]Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits 46(12): 2834-2844 (2011) - [c7]Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC 2011: 184-186 - 2010
- [j9]Imran Ahmed, Jan Mulder, David A. Johns:
A Low-Power Capacitive Charge Pump Based Pipelined ADC. IEEE J. Solid State Circuits 45(5): 1016-1027 (2010)
2000 – 2009
- 2009
- [j8]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3285-3293 (2009) - [c6]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. ISSCC 2009: 74-75 - [c5]Imran Ahmed, Jan Mulder, David A. Johns:
A 50MS/s 9.9mW pipelined ADC with 58dB SNDR in 0.18µm CMOS using capacitive charge-pumps. ISSCC 2009: 164-165 - 2005
- [j7]Jasper Bedaux, Leendert Van Gastel, Piet Blankert, Jan Mulder, Jeroen Verschuur, Wopke Wijngaard:
The e-Xperimenteren+ Project: Pool of Remote Experiments and Software Environment. Int. J. Online Eng. 1(2) (2005) - 2004
- [j6]Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes:
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. IEEE J. Solid State Circuits 39(12): 2116-2125 (2004) - 2001
- [c4]Wouter A. Serdijn, Jan Mulder, Daniel Rocha, Luís Cléber C. Marques:
Advances in low-voltage ultra-low-power analog circuit design. ICECS 2001: 1533-1536
1990 – 1999
- 1999
- [c3]Michiel H. L. Kouwenhoven, Jan Mulder, Wouter A. Serdijn, Arthur H. M. van Roermund:
Analysis of noise in higher-order translinear filters. ISCAS (6) 1999: 61-64 - [c2]Wouter A. Serdijn, Jan Mulder, Michiel H. L. Kouwenhoven, Arthur H. M. van Roermund:
A low-voltage translinear second-order quadrature oscillator. ISCAS (2) 1999: 701-704 - 1998
- [j5]Wouter A. Serdijn, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund:
A wide-tunable translinear second-order oscillator. IEEE J. Solid State Circuits 33(2): 195-201 (1998) - [j4]L. P. L. van Dijk, Albert C. van der Woerd, Jan Mulder, Arthur H. M. van Roermund:
An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids. IEEE J. Solid State Circuits 33(2): 291-294 (1998) - [c1]Dorra Masmoudi, Wouter A. Serdijn, Jan Mulder, Albert C. van der Woerd, Jean Tomas, Jean Paul Dom:
A new current mode synthesis method for dynamic translinear filters and its application in hearing aids. ICECS 1998: 337-340 - 1997
- [j3]Jan Mulder, Marcel van de Gevel, Arthur H. M. van Roermund:
A reduced-area low-power low-voltage single-ended differential pair. IEEE J. Solid State Circuits 32(2): 254-257 (1997) - [j2]Wouter A. Serdijn, Martijn Broest, Jan Mulder, Albert C. van der Woerd, Arthur H. M. van Roermund:
A low-voltage ultra-low-power translinear integrator for audio filter applications. IEEE J. Solid State Circuits 32(4): 577-581 (1997) - [j1]Jan Mulder, Albert C. van der Woerd, Wouter A. Serdijn, Arthur H. M. van Roermund:
An RMS-DC converter based on the dynamic translinear principle. IEEE J. Solid State Circuits 32(7): 1146-1150 (1997)
Coauthor Index
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