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Database: dblp computer science bibliography
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TY - JOUR
ID - DBLP:journals/cal/ParkPASLBB24
AU - Park, Yongmo
AU - Pal, Subhankar
AU - Amarnath, Aporva
AU - Swaminathan, Karthik
AU - Lu, Wei D.
AU - Buyuktosunoglu, Alper
AU - Bose, Pradip
TI - Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms.
JO - IEEE Comput. Archit. Lett.
VL - 23
IS - 1
SP - 108
EP - 111
PY - 2024//
DO - 10.1109/LCA.2024.3381452
UR - https://doi.org/10.1109/LCA.2024.3381452
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2405-09654
AU - Jana, Tapan
AU - Pal, Subhankar
AU - Shaw, Amit
AU - Ramachandra, L. S.
TI - A remedy to mitigate tensile instability in SPH for simulating large deformation and failure of geomaterials.
JO - CoRR
VL - abs/2405.09654
PY - 2024//
DO - 10.48550/ARXIV.2405.09654
UR - https://doi.org/10.48550/arXiv.2405.09654
ER -
TY - CPAPER
ID - DBLP:conf/esorics/AharoniBBBDPPSSSV23
AU - Aharoni, Ehud
AU - Baruch, Moran
AU - Bose, Pradip
AU - Buyuktosunoglu, Alper
AU - Drucker, Nir
AU - Pal, Subhankar
AU - Pelleg, Tomer
AU - Sarpatwar, Kanthi K.
AU - Shaul, Hayim
AU - Soceanu, Omri
AU - Vaculín, Roman
TI - Efficient Pruning for Machine Learning Under Homomorphic Encryption.
BT - Computer Security - ESORICS 2023 - 28th European Symposium on Research in Computer Security, The Hague, The Netherlands, September 25-29, 2023, Proceedings, Part IV
SP - 204
EP - 225
PY - 2023//
DO - 10.1007/978-3-031-51482-1_11
UR - https://doi.org/10.1007/978-3-031-51482-1_11
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2301-08051
AU - Khoshkholghi, Mohammad Ali
AU - Mahmoodi, Toktam
AU - Pal, Subhankar
AU - Chopra, Subhash
AU - Tendulkar, Mayuri
AU - Sarkar, Sandip
TI - xURLCC in 6g with meshed RAN.
JO - CoRR
VL - abs/2301.08051
PY - 2023//
DO - 10.48550/ARXIV.2301.08051
UR - https://doi.org/10.48550/arXiv.2301.08051
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2301-12312
AU - Yang, Yichen
AU - Li, Jingtao
AU - Talati, Nishil
AU - Pal, Subhankar
AU - Feng, Siying
AU - Chakrabarti, Chaitali
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
TI - Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher.
JO - CoRR
VL - abs/2301.12312
PY - 2023//
DO - 10.48550/ARXIV.2301.12312
UR - https://doi.org/10.48550/arXiv.2301.12312
ER -
TY - JOUR
ID - DBLP:journals/jetc/BagherzadehATPD22
AU - Bagherzadeh, Javad
AU - Amarnath, Aporva
AU - Tan, Jielun
AU - Pal, Subhankar
AU - Dreslinski, Ronald G.
TI - A Holistic Solution for Reliability of 3D Parallel Systems.
JO - ACM J. Emerg. Technol. Comput. Syst.
VL - 18
IS - 1
SP - 23:1
EP - 23:27
PY - 2022//
DO - 10.1145/3488900
UR - https://doi.org/10.1145/3488900
ER -
TY - JOUR
ID - DBLP:journals/jssc/KimFDCTPAXMCBDK22
AU - Kim, Sung
AU - Fayazi, Morteza
AU - Daftardar, Alhad
AU - Chen, Kuan-Yu
AU - Tan, Jielun
AU - Pal, Subhankar
AU - Ajayi, Tutu
AU - Xiong, Yan
AU - Mudge, Trevor N.
AU - Chakrabarti, Chaitali
AU - Blaauw, David T.
AU - Dreslinski, Ronald G.
AU - Kim, Hun-Seok
TI - Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory.
JO - IEEE J. Solid State Circuits
VL - 57
IS - 4
SP - 986
EP - 998
PY - 2022//
DO - 10.1109/JSSC.2022.3140241
UR - https://doi.org/10.1109/JSSC.2022.3140241
ER -
TY - JOUR
ID - DBLP:journals/tecs/PalVSG22
AU - Pal, Subhankar
AU - Venkataramani, Swagath
AU - Srinivasan, Viji
AU - Gopalakrishnan, Kailash
TI - OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators.
JO - ACM Trans. Embed. Comput. Syst.
VL - 21
IS - 6
SP - 86:1
EP - 86:29
PY - 2022/11/
DO - 10.1145/3530909
UR - https://doi.org/10.1145/3530909
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2203-13396
AU - Amarnath, Aporva
AU - Pal, Subhankar
AU - Kassa, Hiwot
AU - Vega, Augusto
AU - Buyuktosunoglu, Alper
AU - Franke, Hubertus
AU - Wellman, John-David
AU - Dreslinski, Ronald G.
AU - Bose, Pradip
TI - HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs.
JO - CoRR
VL - abs/2203.13396
PY - 2022//
DO - 10.48550/ARXIV.2203.13396
UR - https://doi.org/10.48550/arXiv.2203.13396
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2207-03384
AU - Aharoni, Ehud
AU - Baruch, Moran
AU - Bose, Pradip
AU - Buyuktosunoglu, Alper
AU - Drucker, Nir
AU - Pal, Subhankar
AU - Pelleg, Tomer
AU - Sarpatwar, Kanthi K.
AU - Shaul, Hayim
AU - Soceanu, Omri
AU - Vaculín, Roman
TI - HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion.
JO - CoRR
VL - abs/2207.03384
PY - 2022//
DO - 10.48550/ARXIV.2207.03384
UR - https://doi.org/10.48550/arXiv.2207.03384
ER -
TY - THES
ID - DBLP:phd/us/Pal21
AU - Pal, Subhankar
TI - Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware.
PY - 2021//
UR - https://hdl.handle.net/2027.42/169859
ER -
TY - JOUR
ID - DBLP:journals/cal/AmarnathPKVBFWD21
AU - Amarnath, Aporva
AU - Pal, Subhankar
AU - Kassa, Hiwot Tadese
AU - Vega, Augusto
AU - Buyuktosunoglu, Alper
AU - Franke, Hubertus
AU - Wellman, John-David
AU - Dreslinski, Ronald, Jr.
AU - Bose, Pradip
TI - Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles.
JO - IEEE Comput. Archit. Lett.
VL - 20
IS - 2
SP - 82
EP - 85
PY - 2021//
DO - 10.1109/LCA.2021.3085505
UR - https://doi.org/10.1109/LCA.2021.3085505
ER -
TY - CPAPER
ID - DBLP:conf/dac/FengSPHKPMMCOCD21
AU - Feng, Siying
AU - Sun, Jiawen
AU - Pal, Subhankar
AU - He, Xin
AU - Kaszyk, Kuba
AU - Park, Dong-Hyeon
AU - Morton, John Magnus
AU - Mudge, Trevor N.
AU - Cole, Murray
AU - O'Boyle, Michael F. P.
AU - Chakrabarti, Chaitali
AU - Dreslinski, Ronald G.
TI - CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics.
BT - 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021
SP - 949
EP - 954
PY - 2021//
DO - 10.1109/DAC18074.2021.9586114
UR - https://doi.org/10.1109/DAC18074.2021.9586114
ER -
TY - CPAPER
ID - DBLP:conf/ispass/PalVSG21
AU - Pal, Subhankar
AU - Venkataramani, Swagath
AU - Srinivasan, Viji
AU - Gopalakrishnan, Kailash
TI - Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators.
BT - IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021
SP - 240
EP - 242
PY - 2021//
DO - 10.1109/ISPASS51385.2021.00046
UR - https://doi.org/10.1109/ISPASS51385.2021.00046
ER -
TY - CPAPER
ID - DBLP:conf/micro/PalAFODD21
AU - Pal, Subhankar
AU - Amarnath, Aporva
AU - Feng, Siying
AU - O'Boyle, Michael F. P.
AU - Dreslinski, Ronald G.
AU - Dubach, Christophe
TI - SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator.
BT - MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, Virtual Event, Greece, October 18-22, 2021
SP - 1005
EP - 1021
PY - 2021//
DO - 10.1145/3466752.3480134
UR - https://doi.org/10.1145/3466752.3480134
ER -
TY - CPAPER
ID - DBLP:conf/vlsic/KimFDCTPAXMCBDK21
AU - Kim, Sung
AU - Fayazi, Morteza
AU - Daftardar, Alhad
AU - Chen, Kuan-Yu
AU - Tan, Jielun
AU - Pal, Subhankar
AU - Ajayi, Tutu
AU - Xiong, Yan
AU - Mudge, Trevor N.
AU - Chakrabarti, Chaitali
AU - Blaauw, David T.
AU - Dreslinski, Ronald G.
AU - Kim, Hun-Seok
TI - Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
BT - 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021
SP - 1
EP - 2
PY - 2021//
DO - 10.23919/VLSICIRCUITS52068.2021.9492391
UR - https://doi.org/10.23919/VLSICircuits52068.2021.9492391
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2109-03024
AU - Kim, Sung
AU - Fayazi, Morteza
AU - Daftardar, Alhad
AU - Chen, Kuan-Yu
AU - Tan, Jielun
AU - Pal, Subhankar
AU - Ajayi, Tutu
AU - Xiong, Yan
AU - Mudge, Trevor N.
AU - Chakrabarti, Chaitali
AU - Blaauw, David T.
AU - Dreslinski, Ronald G.
AU - Kim, Hun-Seok
TI - Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm.
JO - CoRR
VL - abs/2109.03024
PY - 2021//
UR - https://arxiv.org/abs/2109.03024
ER -
TY - JOUR
ID - DBLP:journals/jssc/ParkPFGTRXZAWBC20
AU - Park, Dong-Hyeon
AU - Pal, Subhankar
AU - Feng, Siying
AU - Gao, Paul
AU - Tan, Jielun
AU - Rovinski, Austin
AU - Xie, Shaolin
AU - Zhao, Chun
AU - Amarnath, Aporva
AU - Wesley, Timothy
AU - Beaumont, Jonathan
AU - Chen, Kuan-Yu
AU - Chakrabarti, Chaitali
AU - Taylor, Michael Bedford
AU - Mudge, Trevor N.
AU - Blaauw, David T.
AU - Kim, Hun-Seok
AU - Dreslinski, Ronald G.
TI - A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator.
JO - IEEE J. Solid State Circuits
VL - 55
IS - 4
SP - 933
EP - 944
PY - 2020//
DO - 10.1109/JSSC.2019.2960480
UR - https://doi.org/10.1109/JSSC.2019.2960480
ER -
TY - CPAPER
ID - DBLP:conf/IEEEpact/PalFPKAYHBMXKMS20
AU - Pal, Subhankar
AU - Feng, Siying
AU - Park, Dong-Hyeon
AU - Kim, Sung
AU - Amarnath, Aporva
AU - Yang, Chi-Sheng
AU - He, Xin
AU - Beaumont, Jonathan
AU - May, Kyle
AU - Xiong, Yan
AU - Kaszyk, Kuba
AU - Morton, John Magnus
AU - Sun, Jiawen
AU - O'Boyle, Michael F. P.
AU - Cole, Murray
AU - Chakrabarti, Chaitali
AU - Blaauw, David T.
AU - Kim, Hun-Seok
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
TI - Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration.
BT - PACT '20: International Conference on Parallel Architectures and Compilation Techniques, Virtual Event, GA, USA, October 3-7, 2020
SP - 175
EP - 190
PY - 2020//
DO - 10.1145/3410463.3414627
UR - https://doi.org/10.1145/3410463.3414627
ER -
TY - CPAPER
ID - DBLP:conf/dac/BagherzadehATPD20
AU - Bagherzadeh, Javad
AU - Amarnath, Aporva
AU - Tan, Jielun
AU - Pal, Subhankar
AU - Dreslinski, Ronald G.
TI - R2D3: A Reliability Engine for 3D Parallel Systems.
BT - 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020
SP - 1
EP - 6
PY - 2020//
DO - 10.1109/DAC18072.2020.9218497
UR - https://doi.org/10.1109/DAC18072.2020.9218497
ER -
TY - CPAPER
ID - DBLP:conf/icassp/SoorishettyZPBK20
AU - Soorishetty, A.
AU - Zhou, Jian
AU - Pal, Subhankar
AU - Blaauw, David T.
AU - Kim, H.
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
AU - Chakrabarti, Chaitali
TI - Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture.
BT - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2020, Barcelona, Spain, May 4-8, 2020
SP - 1558
EP - 1562
PY - 2020//
DO - 10.1109/ICASSP40776.2020.9054126
UR - https://doi.org/10.1109/ICASSP40776.2020.9054126
ER -
TY - CPAPER
ID - DBLP:conf/ics/HePAFPRYCDM20
AU - He, Xin
AU - Pal, Subhankar
AU - Amarnath, Aporva
AU - Feng, Siying
AU - Park, Dong-Hyeon
AU - Rovinski, Austin
AU - Ye, Haojie
AU - Chen, Kuan-Yu
AU - Dreslinski, Ronald G.
AU - Mudge, Trevor N.
TI - Sparse-TPU: adapting systolic arrays for sparse matrices.
BT - ICS '20: 2020 International Conference on Supercomputing, Barcelona Spain, June, 2020
SP - 19:1
EP - 19:12
PY - 2020//
DO - 10.1145/3392717.3392751
UR - https://doi.org/10.1145/3392717.3392751
ER -
TY - CPAPER
ID - DBLP:conf/iiswc/PalKFFCOMD20
AU - Pal, Subhankar
AU - Kaszyk, Kuba
AU - Feng, Siying
AU - Franke, Björn
AU - Cole, Murray
AU - O'Boyle, Michael F. P.
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
TI - HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework.
BT - IEEE International Symposium on Workload Characterization, IISWC 2020, Beijing, China, October 27-30, 2020
SP - 13
EP - 24
PY - 2020//
DO - 10.1109/IISWC50251.2020.00011
UR - https://doi.org/10.1109/IISWC50251.2020.00011
ER -
TY - CPAPER
ID - DBLP:conf/iscas/Xiong0PBKMDC20
AU - Xiong, Yan
AU - Zhou, Jian
AU - Pal, Subhankar
AU - Blaauw, David T.
AU - Kim, Hun-Seok
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
AU - Chakrabarti, Chaitali
TI - Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture.
BT - IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020
SP - 1
EP - 5
PY - 2020//
DO - 10.1109/ISCAS45731.2020.9180871
UR - https://doi.org/10.1109/ISCAS45731.2020.9180871
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2007-14371
AU - Vega, Augusto
AU - Amarnath, Aporva
AU - Wellman, John-David
AU - Kassa, Hiwot
AU - Pal, Subhankar
AU - Franke, Hubertus
AU - Buyuktosunoglu, Alper
AU - Dreslinski, Ronald G.
AU - Bose, Pradip
TI - STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors.
JO - CoRR
VL - abs/2007.14371
PY - 2020//
UR - https://arxiv.org/abs/2007.14371
ER -
TY - CPAPER
ID - DBLP:conf/ispass/FengPYD19
AU - Feng, Siying
AU - Pal, Subhankar
AU - Yang, Yichen
AU - Dreslinski, Ronald G.
TI - Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective.
BT - IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2019, Madison, WI, USA, March 24-26, 2019
SP - 202
EP - 211
PY - 2019//
DO - 10.1109/ISPASS.2019.00033
UR - https://doi.org/10.1109/ISPASS.2019.00033
ER -
TY - CPAPER
ID - DBLP:conf/vlsic/PalPFGTRXZAWBCC19
AU - Pal, Subhankar
AU - Park, Dong-Hyeon
AU - Feng, Siying
AU - Gao, Paul
AU - Tan, Jielun
AU - Rovinski, Austin
AU - Xie, Shaolin
AU - Zhao, Chun
AU - Amarnath, Aporva
AU - Wesley, Timothy
AU - Beaumont, Jonathan
AU - Chen, Kuan-Yu
AU - Chakrabarti, Chaitali
AU - Taylor, Michael B.
AU - Mudge, Trevor N.
AU - Blaauw, David T.
AU - Kim, Hun-Seok
AU - Dreslinski, Ronald G.
TI - A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm.
BT - 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019
SP - 150
EP -
PY - 2019//
DO - 10.23919/VLSIC.2019.8778147
UR - https://doi.org/10.23919/VLSIC.2019.8778147
ER -
TY - CPAPER
ID - DBLP:conf/hpca/PalBPAFCKBMD18
AU - Pal, Subhankar
AU - Beaumont, Jonathan
AU - Park, Dong-Hyeon
AU - Amarnath, Aporva
AU - Feng, Siying
AU - Chakrabarti, Chaitali
AU - Kim, Hun-Seok
AU - Blaauw, David T.
AU - Mudge, Trevor N.
AU - Dreslinski, Ronald G.
TI - OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator.
BT - IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018
SP - 724
EP - 736
PY - 2018//
DO - 10.1109/HPCA.2018.00067
UR - https://doi.org/10.1109/HPCA.2018.00067
UR - https://doi.ieeecomputersociety.org/10.1109/HPCA.2018.00067
ER -
TY - CPAPER
ID - DBLP:conf/islped/AmarnathFPARD17
AU - Amarnath, Aporva
AU - Feng, Siying
AU - Pal, Subhankar
AU - Ajayi, Tutu
AU - Rovinski, Austin
AU - Dreslinski, Ronald G.
TI - A carbon nanotube transistor based RISC-V processor using pass transistor logic.
BT - 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017
SP - 1
EP - 6
PY - 2017//
DO - 10.1109/ISLPED.2017.8009156
UR - https://doi.org/10.1109/ISLPED.2017.8009156
ER -
TY - CPAPER
ID - DBLP:conf/ised/PalVPVM14
AU - Pal, Subhankar
AU - Vudadha, Chetan
AU - Phaneendra, P. Sai
AU - Veeramachaneni, Sreehari
AU - Mandalika, Srinivas B.
TI - A New Design of an N-Bit Reversible Arithmetic Logic Unit.
BT - 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014
SP - 224
EP - 225
PY - 2014//
DO - 10.1109/ISED.2014.56
UR - https://doi.org/10.1109/ISED.2014.56
ER -
