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ORCIDSubhankar Pal
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2020 – today
- 2024
[j6]Yongmo Park
, Subhankar Pal, Aporva Amarnath, Karthik Swaminathan, Wei D. Lu, Alper Buyuktosunoglu, Pradip Bose:
Dramaton: A Near-DRAM Accelerator for Large Number Theoretic Transforms. IEEE Comput. Archit. Lett. 23(1): 108-111 (2024)- [i7]Tapan Jana, Subhankar Pal, Amit Shaw, L. S. Ramachandra:
A remedy to mitigate tensile instability in SPH for simulating large deformation and failure of geomaterials. CoRR abs/2405.09654 (2024) - 2023
- [c16]Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín:
Efficient Pruning for Machine Learning Under Homomorphic Encryption. ESORICS (4) 2023: 204-225 - [i6]Mohammad Ali Khoshkholghi, Toktam Mahmoodi, Subhankar Pal, Subhash Chopra, Mayuri Tendulkar, Sandip Sarkar:
xURLCC in 6g with meshed RAN. CoRR abs/2301.08051 (2023) - [i5]Yichen Yang, Jingtao Li, Nishil Talati, Subhankar Pal, Siying Feng, Chaitali Chakrabarti, Trevor N. Mudge, Ronald G. Dreslinski:
Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher. CoRR abs/2301.12312 (2023) - 2022
- [j5]Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski:
A Holistic Solution for Reliability of 3D Parallel Systems. ACM J. Emerg. Technol. Comput. Syst. 18(1): 23:1-23:27 (2022) - [j4]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57(4): 986-998 (2022) - [j3]Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan:
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators. ACM Trans. Embed. Comput. Syst. 21(6): 86:1-86:29 (2022) - [i4]Aporva Amarnath, Subhankar Pal, Hiwot Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald G. Dreslinski, Pradip Bose:
HetSched: Quality-of-Mission Aware Scheduling for Autonomous Vehicle SoCs. CoRR abs/2203.13396 (2022) - [i3]Ehud Aharoni, Moran Baruch, Pradip Bose, Alper Buyuktosunoglu, Nir Drucker, Subhankar Pal, Tomer Pelleg, Kanthi K. Sarpatwar, Hayim Shaul, Omri Soceanu, Roman Vaculín:
HE-PEx: Efficient Machine Learning under Homomorphic Encryption using Pruning, Permutation and Expansion. CoRR abs/2207.03384 (2022) - 2021
- [b1]Subhankar Pal:
Towards Closing the Programmability-Efficiency Gap using Software-Defined Hardware. University of Michigan, USA, 2021 - [j2]Aporva Amarnath, Subhankar Pal, Hiwot Tadese Kassa, Augusto Vega, Alper Buyuktosunoglu, Hubertus Franke, John-David Wellman, Ronald Dreslinski Jr., Pradip Bose:
Heterogeneity-Aware Scheduling on SoCs for Autonomous Vehicles. IEEE Comput. Archit. Lett. 20(2): 82-85 (2021) - [c15]Siying Feng, Jiawen Sun, Subhankar Pal, Xin He, Kuba Kaszyk, Dong-Hyeon Park, John Magnus Morton, Trevor N. Mudge, Murray Cole, Michael F. P. O'Boyle, Chaitali Chakrabarti, Ronald G. Dreslinski:
CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. DAC 2021: 949-954 - [c14]Subhankar Pal, Swagath Venkataramani, Viji Srinivasan, Kailash Gopalakrishnan:
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators. ISPASS 2021: 240-242 - [c13]Subhankar Pal, Aporva Amarnath, Siying Feng, Michael F. P. O'Boyle, Ronald G. Dreslinski, Christophe Dubach:
SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator. MICRO 2021: 1005-1021 - [c12]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits 2021: 1-2 - [i2]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR abs/2109.03024 (2021) - 2020
- [j1]Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits 55(4): 933-944 (2020) - [c11]Subhankar Pal, Siying Feng, Dong-Hyeon Park, Sung Kim, Aporva Amarnath, Chi-Sheng Yang, Xin He, Jonathan Beaumont, Kyle May, Yan Xiong, Kuba Kaszyk, John Magnus Morton, Jiawen Sun, Michael F. P. O'Boyle, Murray Cole, Chaitali Chakrabarti, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski:
Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. PACT 2020: 175-190 - [c10]Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski:
R2D3: A Reliability Engine for 3D Parallel Systems. DAC 2020: 1-6 - [c9]A. Soorishetty, Jian Zhou, Subhankar Pal, David T. Blaauw, H. Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti:
Accelerating Linear Algebra Kernels on a Massively Parallel Reconfigurable Architecture. ICASSP 2020: 1558-1562 - [c8]Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge:
Sparse-TPU: adapting systolic arrays for sparse matrices. ICS 2020: 19:1-19:12 - [c7]Subhankar Pal, Kuba Kaszyk, Siying Feng, Björn Franke, Murray Cole, Michael F. P. O'Boyle, Trevor N. Mudge, Ronald G. Dreslinski:
HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. IISWC 2020: 13-24 - [c6]Yan Xiong, Jian Zhou, Subhankar Pal, David T. Blaauw, Hun-Seok Kim, Trevor N. Mudge, Ronald G. Dreslinski, Chaitali Chakrabarti:
Accelerating Deep Neural Network Computation on a Low Power Reconfigurable Architecture. ISCAS 2020: 1-5 - [i1]Augusto Vega, Aporva Amarnath, John-David Wellman, Hiwot Kassa, Subhankar Pal, Hubertus Franke, Alper Buyuktosunoglu, Ronald G. Dreslinski, Pradip Bose:
STOMP: A Tool for Evaluation of Scheduling Policies in Heterogeneous Multi-Processors. CoRR abs/2007.14371 (2020)
2010 – 2019
- 2019
- [c5]Siying Feng, Subhankar Pal, Yichen Yang, Ronald G. Dreslinski:
Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. ISPASS 2019: 202-211 - [c4]Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits 2019: 150- - 2018
- [c3]Subhankar Pal, Jonathan Beaumont, Dong-Hyeon Park, Aporva Amarnath, Siying Feng, Chaitali Chakrabarti, Hun-Seok Kim, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski:
OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator. HPCA 2018: 724-736 - 2017
- [c2]Aporva Amarnath, Siying Feng, Subhankar Pal, Tutu Ajayi, Austin Rovinski, Ronald G. Dreslinski:
A carbon nanotube transistor based RISC-V processor using pass transistor logic. ISLPED 2017: 1-6 - 2014
- [c1]Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika:
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED 2014: 224-225
Coauthor Index
aka: Ronald Dreslinski Jr.
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last updated on 2024-10-07 21:22 CEST by the dblp team
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