Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
Content:text/plain; charset="utf-8"
TY - CPAPER
ID - DBLP:conf/micro/HaghiWALGHLG24
AU - Haghi, Pouya
AU - Wu, Chunshu
AU - Azad, Zahra
AU - Li, Yanfei
AU - Gui, Andrew
AU - Hao, Yuchen
AU - Li, Ang
AU - Geng, Tony Tong
TI - Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign.
BT - 57th IEEE/ACM International Symposium on Microarchitecture, MICRO 2024, Austin, TX, USA, November 2-6, 2024
SP - 1617
EP - 1631
PY - 2024//
DO - 10.1109/MICRO61859.2024.00118
UR - https://doi.org/10.1109/MICRO61859.2024.00118
ER -
TY - JOUR
ID - DBLP:journals/tvlsi/AzadYAPTJ23
AU - Azad, Zahra
AU - Yang, Guowei
AU - Agrawal, Rashmi
AU - Petrisko, Daniel
AU - Taylor, Michael Bedford
AU - Joshi, Ajay
TI - RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.
JO - IEEE Trans. Very Large Scale Integr. Syst.
VL - 31
IS - 10
SP - 1523
EP - 1536
PY - 2023/10/
DO - 10.1109/TVLSI.2023.3288754
UR - https://doi.org/10.1109/TVLSI.2023.3288754
UR - https://www.wikidata.org/entity/Q122943341
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/abs-2302-07104
AU - Azad, Zahra
AU - Yang, Guowei
AU - Agrawal, Rashmi
AU - Petrisko, Daniel
AU - Taylor, Michael B.
AU - Joshi, Ajay
TI - RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption.
JO - CoRR
VL - abs/2302.07104
PY - 2023//
DO - 10.48550/ARXIV.2302.07104
UR - https://doi.org/10.48550/arXiv.2302.07104
ER -
TY - CPAPER
ID - DBLP:conf/islped/AzadYAPTJ22
AU - Azad, Zahra
AU - Yang, Guowei
AU - Agrawal, Rashmi
AU - Petrisko, Daniel
AU - Taylor, Michael B.
AU - Joshi, Ajay
TI - RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation.
BT - ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1 - 3, 2022
SP - 13:1
EP - 13:6
PY - 2022//
DO - 10.1145/3531437.3539725
UR - https://doi.org/10.1145/3531437.3539725
ER -
TY - CPAPER
ID - DBLP:conf/ispass/BuchAJR21
AU - Buch, Michael
AU - Azad, Zahra
AU - Joshi, Ajay
AU - Reddi, Vijay Janapa
TI - AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones.
BT - IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021
SP - 96
EP - 106
PY - 2021//
DO - 10.1109/ISPASS51385.2021.00027
UR - https://doi.org/10.1109/ISPASS51385.2021.00027
ER -
TY - CPAPER
ID - DBLP:conf/ispass/AzadSPJ21
AU - Azad, Zahra
AU - Sen, Rathijit
AU - Park, Kwanghyun
AU - Joshi, Ajay
TI - Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads?
BT - IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021
SP - 243
EP - 253
PY - 2021//
DO - 10.1109/ISPASS51385.2021.00047
UR - https://doi.org/10.1109/ISPASS51385.2021.00047
ER -
TY - JOUR
ID - DBLP:journals/micro/PetriskoGWJDGZA20
AU - Petrisko, Daniel
AU - Gilani, Farzam
AU - Wyse, Mark
AU - Jung, Dai Cheol
AU - Davidson, Scott
AU - Gao, Paul
AU - Zhao, Chun
AU - Azad, Zahra
AU - Canakci, Sadullah
AU - Veluri, Bandhav
AU - Guarino, Tavio
AU - Joshi, Ajay
AU - Oskin, Mark
AU - Taylor, Michael Bedford
TI - BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.
JO - IEEE Micro
VL - 40
IS - 4
SP - 93
EP - 102
PY - 2020//
DO - 10.1109/MM.2020.2996145
UR - https://doi.org/10.1109/MM.2020.2996145
UR - https://www.wikidata.org/entity/Q114987433
ER -
TY - JOUR
ID - DBLP:journals/tetc/AzadFMM19
AU - Azad, Zahra
AU - Farbeh, Hamed
AU - Monazzah, Amir Mahdi Hosseini
AU - Miremadi, Seyed Ghassem
TI - AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches.
JO - IEEE Trans. Emerg. Top. Comput.
VL - 7
IS - 3
SP - 481
EP - 492
PY - 2019//
DO - 10.1109/TETC.2017.2701880
UR - https://doi.org/10.1109/TETC.2017.2701880
ER -
TY - CPAPER
ID - DBLP:conf/date/AzadFM18
AU - Azad, Zahra
AU - Farbeh, Hamed
AU - Monazzah, Amir Mahdi Hosseini
TI - ORIENT: Organized interleaved ECCs for new STT-MRAM caches.
BT - 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018
SP - 1187
EP - 1190
PY - 2018//
DO - 10.23919/DATE.2018.8342194
UR - https://doi.org/10.23919/DATE.2018.8342194
ER -
TY - JOUR
ID - DBLP:journals/tpds/AzadFMM17
AU - Azad, Zahra
AU - Farbeh, Hamed
AU - Monazzah, Amir Mahdi Hosseini
AU - Miremadi, Seyed Ghassem
TI - An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors.
JO - IEEE Trans. Parallel Distributed Syst.
VL - 28
IS - 6
SP - 1564
EP - 1577
PY - 2017//
DO - 10.1109/TPDS.2016.2628742
UR - https://doi.org/10.1109/TPDS.2016.2628742
UR - http://doi.ieeecomputersociety.org/10.1109/TPDS.2016.2628742
ER -
