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ORCIDZahra Azad
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2020 – today
- 2024
[c5]Pouya Haghi, Chunshu Wu, Zahra Azad, Yanfei Li, Andrew Gui, Yuchen Hao, Ang Li, Tony Tong Geng:
Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign. MICRO 2024: 1617-1631- 2023
- [j4]Zahra Azad
, Guowei Yang, Rashmi Agrawal, Daniel Petrisko, Michael Bedford Taylor, Ajay Joshi:
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1523-1536 (2023) - [i1]Zahra Azad, Guowei Yang, Rashmi Agrawal, Daniel Petrisko, Michael B. Taylor, Ajay Joshi:
RISE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Encryption. CoRR abs/2302.07104 (2023) - 2022
- [c4]Zahra Azad, Guowei Yang, Rashmi Agrawal, Daniel Petrisko, Michael B. Taylor, Ajay Joshi:
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation. ISLPED 2022: 13:1-13:6 - 2021
- [c3]Michael Buch, Zahra Azad, Ajay Joshi, Vijay Janapa Reddi:
AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones. ISPASS 2021: 96-106 - [c2]Zahra Azad, Rathijit Sen, Kwanghyun Park, Ajay Joshi:
Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads? ISPASS 2021: 243-253 - 2020
- [j3]Daniel Petrisko, Farzam Gilani, Mark Wyse, Dai Cheol Jung, Scott Davidson, Paul Gao, Chun Zhao, Zahra Azad, Sadullah Canakci, Bandhav Veluri, Tavio Guarino, Ajay Joshi, Mark Oskin, Michael Bedford Taylor:
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. IEEE Micro 40(4): 93-102 (2020)
2010 – 2019
- 2019
- [j2]Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi:
AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches. IEEE Trans. Emerg. Top. Comput. 7(3): 481-492 (2019) - 2018
- [c1]Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah:
ORIENT: Organized interleaved ECCs for new STT-MRAM caches. DATE 2018: 1187-1190 - 2017
- [j1]Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi:
An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors. IEEE Trans. Parallel Distributed Syst. 28(6): 1564-1577 (2017)
Coauthor Index
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