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ORCIDJeffrey L. Burns
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2010 – 2019
- 2017
[c15]Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash:
Panel discussions: "Cool chips for the next decade". COOL Chips 2017: 1-3- 2011
- [c14]Jeffrey L. Burns:
Technology trends and implications on SoC design. SoCC 2011: 386
2000 – 2009
- 2004
- [j6]Alan J. Drake, Kevin J. Nowka
, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown:
Resonant clocking using distributed parasitic capacitance. IEEE J. Solid State Circuits 39(9): 1520-1528 (2004) - [c13]Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design 2004: 234-239 - 2003
- [c12]Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown:
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC 2003: 313-316 - [c11]Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown:
A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD 2003: 689-692 - [c10]Vikas Chandra, Gary D. Carpenter, Jeffrey L. Burns:
Dynamically Optimized Synchronous Communication for Low Power System on Chip Designs. ICCD 2003: 134-139 - [c9]Juan Antonio Carballo, Jeffrey L. Burns, Seung-Moon Yoo, Ivan Vo, V. Robert Norman:
A semi-custom voltage-island technique and its application to high-speed serial links. ISLPED 2003: 60-65 - [c8]Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns:
Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99 - [c7]Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown:
Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103 - 2002
- [j5]Kevin J. Nowka, Gary D. Carpenter, Eric W. MacDonald, Hung C. Ngo, Bishop Brock, Koji I. Ishii, Tuyet Nguyen, Jeffrey L. Burns:
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE J. Solid State Circuits 37(11): 1441-1447 (2002)
1990 – 1999
- 1999
- [c6]Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns:
Performance Driven Synthesis for Pass-Transistor Logic. VLSI Design 1999: 372-377 - 1998
- [j4]Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric:
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE J. Solid State Circuits 33(11): 1600-1608 (1998) - [j3]H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi:
Designing for a gigahertz [guTS integer processor]. IEEE Micro 18(3): 66-74 (1998) - [j2]Jeffrey L. Burns, Jack A. Feldman:
C5M-a control-logic layout synthesis system for high-performance microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 14-23 (1998) - [c5]Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo:
Design methodology for a 1.0 GHz microprocessor. ICCD 1998: 17-23 - [c4]Rajat Chaudhry, Tai-Hung Liu, Adnan Aziz, Jeffrey L. Burns:
Area-oriented synthesis for pass-transistor logic. ICCD 1998: 160-167 - 1997
- [c3]Jeffrey L. Burns, Jack A. Feldman:
C5M - a control logic layout synthesis system for high-performance microprocessors. ISPD 1997: 110-115 - 1994
- [c2]Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns:
The Effect of Wire Length Minimization on Yield. DFT 1994: 97-105
1980 – 1989
- 1988
- [j1]Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli, Kartikeya Mayaram, Srinivas Devadas, Hi-Keung Tony Ma:
Techniques for multilayer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(6): 698-712 (1988) - 1986
- [c1]Douglas Braun, Jeffrey L. Burns, Srinivas Devadas, Hi-Keung Tony Ma, Kartikeya Mayaram, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli:
Chameleon: a new multi-layer channel router. DAC 1986: 495-502
Coauthor Index
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