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ORCIDXun Jiang 0002
Person information
- affiliation: Peking University, Beijing, China
- affiliation (former): Nanjing University, School of Electronic Science and Engineering, China
Other persons with the same name
- Xun Jiang — disambiguation page
- Xun Jiang 0001
![[0000-0003-2209-651X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0003-2209-651X")
— University of Electronic Science and Technology of China, Chengdu, China
Other persons with a similar name
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2020 – today
- 2024
[c8]Jiarui Wang, Xun Jiang, Yibo Lin:
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. DAC 2024: 17:1-17:6- [c7]Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun:
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. DAC 2024: 31:1-31:6 - [c6]Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. DAC 2024: 36:1-36:6 - [c5]Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. ICLR 2024 - [c4]Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. VLSI Technology and Circuits 2024: 1-2 - [i1]Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang:
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. CoRR abs/2403.18569 (2024) - 2023
- [c3]Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang:
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. DAC 2023: 1-6 - [c2]Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. ICCAD 2023: 1-9 - 2022
- [c1]Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang:
FPGA-Accelerated Maze Routing Kernel for VLSI Designs. ASP-DAC 2022: 592-597
Coauthor Index
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