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dblp: A. Zainuddin https://dblp.org/pid/177/3934.html dblp person page RSS feed Mon, 15 Jul 2024 00:07:44 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: A. Zainuddinhttps://dblp.org/pid/177/3934.html14451 Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs.https://doi.org/10.1109/IRPS.2019.8720535, , , , , , , , , , :
Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs. IRPS : 1-6]]>https://dblp.org/rec/conf/irps/MahmudGTMJSZRCM19Tue, 01 Jan 2019 00:00:00 +0100 Understanding gate metal work function (mWF) impact on device reliability - A holistic approach.https://doi.org/10.1109/IRPS.2018.8353646, , , , , , , , :
Understanding gate metal work function (mWF) impact on device reliability - A holistic approach. IRPS : 6]]>https://dblp.org/rec/conf/irps/SrinivasanRCZKP18Mon, 01 Jan 2018 00:00:00 +0100 A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.https://doi.org/10.1109/VLSIC.2015.7231380, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , :
A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products. VLSIC : 12-]]>https://dblp.org/rec/conf/vlsic/JanACCCDHIJKSKK15Thu, 01 Jan 2015 00:00:00 +0100