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ORCIDSerif Yesil
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2020 – today
- 2023
[c11]Gerasimos Gerogiannis
, Serif Yesil, Damitha Lenadora, Dingyuan Cao, Charith Mendis, Josep Torrellas:
SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM. ISCA 2023: 19:1-19:15- [c10]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning. PPoPP 2023: 329-341 - [i3]Damitha Lenadora, Vimarsh Sathia, Gerasimos Gerogiannis, Serif Yesil, Josep Torrellas, Charith Mendis:
Input-sensitive dense-sparse primitive compositions for GNN acceleration. CoRR abs/2306.15155 (2023) - [i2]Caleb Ju, Serif Yesil, Mengyuan Sun, Chandra Chekuri, Edgar Solomonik:
Efficient parallel implementation of the multiplicative weight update method for graph-based linear programs. CoRR abs/2307.03307 (2023) - 2022
- [j4]Serif Yesil, Ozcan Ozturk:
Scheduling for heterogeneous systems in accelerator-rich environments. J. Supercomput. 78(1): 200-221 (2022) - [c9]Serif Yesil, José E. Moreira, Josep Torrellas:
Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques. ICS 2022: 27:1-27:14 - 2020
- [c8]Azin Heidarshenas, Serif Yesil, Dimitrios Skarlatos, Sasa Misailovic, Adam Morrison, Josep Torrellas:
V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging. ICS 2020: 9:1-9:13 - [c7]Azin Heidarshenas, Tanmay Gangwani, Serif Yesil, Adam Morrison, Josep Torrellas:
Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors. ICS 2020: 18:1-18:13 - [c6]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization. SC 2020: 86
2010 – 2019
- 2019
- [c5]Serif Yesil, Azin Heidarshenas, Adam Morrison, Josep Torrellas:
Understanding priority-based scheduling of graph algorithms on a shared-memory platform. SC 2019: 46:1-46:14 - 2018
- [j3]Serif Yesil, Ismail Akturk, Ulya R. Karpuzcu:
Toward Dynamic Precision Scaling. IEEE Micro 38(4): 30-39 (2018) - [j2]Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven M. Burns, Ozcan Ozturk:
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 420-430 (2018) - 2017
- [j1]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Ozcan Ozturk:
Graph Analytics Accelerators for Cognitive Systems. IEEE Micro 37(1): 42-51 (2017) - [i1]Serif Yesil, Ismail Akturk, Ulya R. Karpuzcu:
On Dynamic Precision Scaling. CoRR abs/1709.06160 (2017) - 2016
- [c4]Serif Yesil, Suleyman Tosun, Özcan Özturk:
FPGA implementation of a fault-tolerant application-specific NoC design. DTIS 2016: 1-6 - [c3]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, John Greth, Steven M. Burns, Özcan Özturk:
Energy Efficient Architecture for Graph Analytics Accelerators. ISCA 2016: 166-177 - 2015
- [c2]Muhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. ICCAD 2015: 676-681 - [c1]Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk:
Hardware Accelerator Design for Data Centers. ICCAD 2015: 770-775
Coauthor Index
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