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ORCIDWilliam Rhett Davis
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2020 – today
- 2024
[c48]Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang:
DE-HNN: An effective neural model for Circuit Netlist representation. AISTATS 2024: 4258-4266- [i3]Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Donghyeon Koh, Michaël Defferrard, Elahe Rezaei, Ryan Carey, W. Rhett Davis, Rajeev Jain, Yusu Wang:
DE-HNN: An effective neural model for Circuit Netlist representation. CoRR abs/2404.00477 (2024) - 2023
- [j13]Luis Francisco
, W. Rhett Davis, Paul D. Franzon:
A Deep Transfer Learning Design Rule Checker With Synthetic Training. IEEE Des. Test 40(1): 77-84 (2023) - 2021
- [c47]Qianli Zhao, W. Rhett Davis:
A Virtual Platform for Object Detection Systems. 3DIC 2021: 1-6 - [c46]W. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain:
Fast and Accurate PPA Modeling with Transfer Learning. ICCAD 2021: 1-8 - [c45]Zhiping Wang, W. Rhett Davis:
An Instruction-Level Power and Energy Model for the Rocket Chip Generator. ISLPED 2021: 1-6 - [c44]Luis Francisco, Paul D. Franzon, W. Rhett Davis:
Fast and Accurate PPA Modeling with Transfer Learning. MLCAD 2021: 1-6 - 2020
- [c43]W. Rhett Davis, Colin Shaw, Ahmed Ramadan Hassan:
How to write a compact reliability model with the Open Model Interface (OMI). IRPS 2020: 1-2 - [c42]Luis Francisco, Tanmay Lagare, Arpit Jain, Somal Chaudhary, Madhura Kulkarni, Divya Sardana, W. Rhett Davis, Paul D. Franzon:
Design Rule Checking with a CNN Based Feature Extractor. MLCAD 2020: 9-14 - [i2]Kirti Bhanushali, Chinmay Tembe, W. Rhett Davis:
Development of a Predictive Process Design kit for15-nm FinFETs: FreePDK15. CoRR abs/2009.04600 (2020) - [i1]Luis Francisco, Tanmay Lagare, Arpit Jain, Somal Chaudhary, Madhura Kulkarni, Divya Sardana, W. Rhett Davis, Paul D. Franzon:
Design Rule Checking with a CNN Based Feature Extractor. CoRR abs/2012.11510 (2020)
2010 – 2019
- 2019
- [j12]Jong Beom Park, William Rhett Davis, Paul D. Franzon:
3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 756-768 (2019) - [c41]T. Robert Harris, W. Rhett Davis, Steven Lipa, W. Shepherd Pitts, Paul D. Franzon:
Vertical Stack Thermal Characterization of Heterogeneous Integration and Packages. 3DIC 2019: 1-3 - [c40]Barkha Gupta, W. Rhett Davis:
Characterization of Fast, Accurate Leakage Power Models for IEEE P2416. ISQED 2019: 39-44 - [c39]Billy Huggins, W. Rhett Davis, Paul D. Franzon:
Estimating Pareto Optimum Fronts to Determine Knob Settings in Electronic Design Automation Tools. ISQED 2019: 304-310 - 2017
- [c38]Vinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor. ICCD 2017: 145-152 - 2016
- [c37]Randy Widialaksono, Rangeen Basu Roy Chowdhury, Zhenqian Zhang, Joshua Schabel, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Physical design of a 3D-stacked heterogeneous multi-core processor. 3DIC 2016: 1-5 - 2015
- [c36]T. Robert Harris, Eric J. Wyers, Lee Wang, Samuel Graham, Georges Pavlidis, Paul D. Franzon, W. Rhett Davis:
Thermal simulation of heterogeneous GaN/ InP/silicon 3DIC stacks. 3DIC 2015: TS10.2.1-TS10.2.4 - [c35]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Marcus Tshibangu, Steve Lipa:
Computing in 3D. 3DIC 2015: TS6.1.1-TS6.1.2 - [c34]Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa:
Computing in 3D. CICC 2015: 1-6 - [c33]Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. Hot Chips Symposium 2015: 1 - [c32]Kirti Bhanushali, W. Rhett Davis:
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology. ISPD 2015: 165-170 - 2014
- [c31]Paul D. Franzon, Eric Rotenberg, James Tuck, Huiyang Zhou, W. Rhett Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, Steve Lipa, Chao Li, Jong Beom Park, Joshua Schabel:
3D-enabled customizable embedded computer (3DECC). 3DIC 2014: 1-3 - [c30]T. Robert Harris, Paul D. Franzon, W. Rhett Davis, Lee Wang:
Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits. 3DIC 2014: 1-3 - [c29]Randy Widialaksono, Wenxu Zhao, W. Rhett Davis, Paul D. Franzon:
Leveraging 3D-IC for on-chip timing uncertainty measurements. 3DIC 2014: 1-4 - [c28]Nagu R. Dhanwada, William Rhett Davis, Jerry Frenkil:
Towards a standard flow for system level power modeling. ICCAD 2014: 73 - [c27]Shivam Priyadarshi, W. Rhett Davis, Paul D. Franzon:
Pathfinder3D: A framework for exploring early thermal tradeoffs in 3DIC. ICICDT 2014: 1-6 - 2013
- [c26]Nyunyi M. Tshibangu, Paul D. Franzon, Eric Rotenberg, William Rhett Davis:
Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 3DIC 2013: 1-4 - [c25]Eric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon:
Rationale for a 3D heterogeneous multi-core processor. ICCD 2013: 154-168 - [c24]Paul D. Franzon, Shivam Priyadarshi, Steve Lipa, W. Rhett Davis, Thorlindur Thorolfsson:
Exploring early design tradeoffs in 3DIC. ISCAS 2013: 545-549 - [c23]Shivam Priyadarshi, Niket K. Choudhary, Brandon H. Dwiel, Ankita Upreti, Eric Rotenberg, William Rhett Davis, Paul D. Franzon:
Hetero2 3D integration: A scheme for optimizing efficiency/cost of Chip Multiprocessors. ISQED 2013: 1-7 - 2012
- [j11]Nagu R. Dhanwada, David J. Hathaway, Jerry Frenkil, W. Rhett Davis, Harun Demircioglu:
Leakage Power Contributor Modeling. IEEE Des. Test Comput. 29(2): 71-78 (2012) - [j10]Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer:
Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. IET Circuits Devices Syst. 6(1): 35-44 (2012) - [j9]Samson Melamed, Thorlindur Thorolfsson, T. Robert Harris, Shivam Priyadarshi, Paul D. Franzon, Michael B. Steer, W. Rhett Davis:
Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 676-689 (2012) - [j8]Shivam Priyadarshi, Christopher S. Saunders, Nikhil Kriplani, Harun Demircioglu, W. Rhett Davis, Paul D. Franzon, Michael B. Steer:
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1522-1535 (2012) - [j7]Nariman Moezzi Madani, Thorlindur Thorolfsson, Patrick Chiang, William Rhett Davis:
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding. J. Signal Process. Syst. 68(2): 171-182 (2012) - 2011
- [c22]Paul D. Franzon, W. Rhett Davis, Zheng Zhou, Shivam Priyadarshi, Matthew Hogan, Tanay Karnik, Ganapti Srinavas:
Coordinating 3D designs: Interface IP, standards or free form? 3DIC 2011: 1-3 - [c21]Shivam Priyadarshi, Jianchen Hu, Won Ha Choi, Samson Melamed, Xi Chen, W. Rhett Davis, Paul D. Franzon:
Pathfinder 3D: A flow for system-level design space exploration. 3DIC 2011: 1-8 - [c20]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson, Samson Melamed:
3D Specific Systems: Design and CAD. Asian Test Symposium 2011: 470-473 - [c19]Nariman Moezzi Madani, Thorlindur Thorolfsson, Joseph Crop, Patrick Chiang, W. Rhett Davis:
An energy-efficient 64-QAM MIMO detector for emerging wireless standards. DATE 2011: 246-251 - [c18]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson, Samson Melamed:
3D specific systems design and CAD. ICSAMOS 2011: 326-329 - [p1]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson:
Design and Computer Aided Design of 3DIC. 3D Integration for NoC-based SoC Architectures 2011: 75-88 - 2010
- [j6]Thorlindur Thorolfsson, Samson Melamed, W. Rhett Davis, Paul D. Franzon:
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration. ACM Trans. Design Autom. Electr. Syst. 16(1): 5:1-5:25 (2010) - [c17]Nariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis:
A low-area flexible MIMO detector for WiFi/WiMAX standards. DATE 2010: 1633-1636 - [c16]Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson:
Creating 3D specific systems: Architecture, design and CAD. DATE 2010: 1684-1688 - [c15]Nariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis:
Algorithm and hardware complexity reduction techniques for k-best sphere decoders. ACM Great Lakes Symposium on VLSI 2010: 471-476
2000 – 2009
- 2009
- [j5]William Rhett Davis, Eun Chu Oh, Ambarish M. Sule, Paul D. Franzon:
Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 496-506 (2009) - [j4]Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser E. Alexander:
Automated Design Space Exploration for DSP Applications. J. Signal Process. Syst. 56(2-3): 199-216 (2009) - [c14]Xi Chen, William Rhett Davis:
Delay analysis and design exploration for 3D SRAM. 3DIC 2009: 1-4 - [c13]Samson Melamed, Thorlindur Thorolfsson, Adi Srinivasan, Edmund Cheng, Paul D. Franzon, William Rhett Davis:
Junction-level thermal extraction and simulation of 3DICs. 3DIC 2009: 1-7 - [c12]Christopher Mineo, William Rhett Davis:
The benefits of 3D networks-on-chip as shown with LDPC decoding. 3DIC 2009: 1-8 - [c11]Nariman Moezzi Madani, William Rhett Davis:
High-throughput low-complexity MIMO detector based on K-best algorithm. ACM Great Lakes Symposium on VLSI 2009: 451-456 - 2008
- [c10]Christopher Mineo, Ravi Jenkal, Samson Melamed, W. Rhett Davis:
Inter-die signaling in three dimensional integrated circuits. CICC 2008: 655-658 - [c9]Paul D. Franzon, W. Rhett Davis, Michael B. Steer, Steve Lipa, Eun Chu Oh, Thorlindur Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller:
Design and CAD for 3D integrated circuits. DAC 2008: 668-673 - 2007
- [c8]Ravi Jenkal, W. Rhett Davis:
An architecture for energy efficient sphere decoding. ISLPED 2007: 244-249 - [c7]James E. Stine, Ivan D. Castellanos, Michael H. Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, Ravi Jenkal:
FreePDK: An Open-Source Variation-Aware Design Kit. MSE 2007: 173-174 - 2006
- [c6]Hao Hua, Christopher Mineo, Kory Schoenfliess, Ambarish M. Sule, Samson Melamed, Ravi Jenkal, W. Rhett Davis:
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. DAC 2006: 997-1002 - [c5]Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser E. Alexander:
Automated Architectural Exploration for Signal Processing Algorithms. SiPS 2006: 274-279 - [c4]Ravi Jenkal, Hao Hua, Ambarish M. Sule, W. Rhett Davis:
Architecture for Energy Efficient Sphere Decoding. SoCC 2006: 267-270 - 2005
- [j3]W. Rhett Davis, John M. Wilson, Stephen E. Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael B. Steer, Paul D. Franzon:
Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des. Test Comput. 22(6): 498-510 (2005) - 2004
- [c3]W. Rhett Davis, Ambarish M. Sule, Hao Hua:
Multi-Parameter Power Minimization of Synthesized Datapaths. ISVLSI 2004: 151-157 - 2003
- [j2]Engling Yeo, Stephanie Augsburger, W. Rhett Davis, Borivoje Nikolic:
A 500-Mb/s soft-output Viterbi decoder. IEEE J. Solid State Circuits 38(7): 1234-1241 (2003) - [c2]W. Rhett Davis:
Getting High-Performance Silicon from System-Level Design. ISVLSI 2003: 238-243 - 2002
- [j1]W. Rhett Davis, Ning Zhang, Kevin Camera, Dejan Markovic, Tina Smilkstein, M. Josie Ammer, Engling Yeo, Stephanie Augsburger, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high-throughput low-power dedicated signal processing systems. IEEE J. Solid State Circuits 37(3): 420-431 (2002) - 2001
- [c1]W. Rhett Davis, Ning Zhang, Kevin Camera, Fred Chen, Dejan Markovic, Nathan Chan, Borivoje Nikolic, Robert W. Brodersen:
A design environment for high throughput, low power dedicated signal processing systems. CICC 2001: 545-548
Coauthor Index
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last updated on 2024-10-07 21:25 CEST by the dblp team
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