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2020 – today
- 2024
[c66]Greg Stitt
, Wesley Piard, Christopher Crary:
Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet. FPGA 2024: 12-21- 2023
- [c65]Christopher Crary, Wesley Piard, Greg Stitt, Caleb Bean, Benjamin M. Hicks:
Using FPGA Devices to Accelerate Tree-Based Genetic Programming: A Preliminary Exploration with Recent Technologies. EuroGP 2023: 182-197 - [c64]Jackson Fugate, Greg Stitt, Naren Vikram Raj Masna, Aritra Dasgupta, Swarup Bhunia, Nij Dorairaj, David Kehlet:
An Exploration of ATPG Methods for Redacted IP and Reconfigurable Hardware. VTS 2023: 1-7 - 2022
- [c63]Christopher Crary, Wesley Piard, Britton Chesley, Greg Stitt:
Work-in-Progress: Toward a Robust, Reconfigurable Hardware Accelerator for Tree-Based Genetic Programming. CASES 2022: 17-18 - 2021
- [j33]Ruben Vazquez, Ayobami S. Edun, Ann Gordon-Ross, Greg Stitt:
Dynamic Scheduling for Heterogeneous Multicores. SN Comput. Sci. 2(6): 486 (2021) - [c62]Sai P. Chenna, Herman Lam, Greg Stitt, S. Balachandar:
Scalable Performance Prediction of Irregular Workloads in Multi-Phase Particle-in-Cell Applications. IPDPS Workshops 2021: 816-825 - 2020
- [j32]Greg Stitt, David Campbell:
PANDORA: An Architecture-Independent Parallelizing Approximation-Discovery Framework. ACM Trans. Embed. Comput. Syst. 19(5): 39:1-39:17 (2020) - [c61]Ryan Blanchard, Greg Stitt, Herman Lam:
FPGA Acceleration of Fluid-Flow Kernels. H2RC@SC 2020: 29-37
2010 – 2019
- 2019
- [c60]Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress. CODES+ISSS 2019: 11:1-11:2 - [c59]Ayobami S. Edun, Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Dynamic Scheduling on Heterogeneous Multicores. DATE 2019: 1685-1690 - [c58]Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Machine Learning-based Prediction for Dynamic Architectural Optimizations. IGSC 2019: 1-6 - [c57]Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Energy Prediction for Cache Tuning in Embedded Systems. ICCD 2019: 630-637 - [c56]Sai P. Chenna, Greg Stitt, Herman Lam:
Multi-Parameter Performance Modeling using Symbolic Regression. HPCS 2019: 312-321 - [c55]Carlo Pascoe, Ryan Blanchard, Herman Lam, Greg Stitt:
A FPGA-Pipelined, High-Throughput Approach to Coarse-Grained Simulation of HPC Systems. HPCS 2019: 674-683 - [c54]Greg Stitt, David Campbell:
PANDORA: a parallelizing approximation-discovery framework (WIP paper). LCTES 2019: 198-202 - [c53]Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Machine Learning-based Prediction for Dynamic, Runtime Architectural Optimizations of Embedded Systems. NORCAS 2019: 1-7 - [c52]David Wilson, Greg Stitt:
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development. ReConFig 2019: 1-8 - 2018
- [c51]Madison N. Emas, Austin Baylis, Greg Stitt:
High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex. FCCM 2018: 97-100 - [c50]Greg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis:
Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA Systems. FPGA 2018: 173-182 - [c49]David Wilson, Greg Stitt, James Coole:
A Recurrently Generated Overlay Architecture for Rapid FPGA Application Development. HEART 2018: 4:1-4:6 - [c48]Ajay Ramaswamy, Nalini Kumar, Aravind Neelakantan, Herman Lam, Greg Stitt:
Scalable Behavioral Emulation of Extreme-Scale Systems Using Structural Simulation Toolkit. ICPP 2018: 17:1-17:11 - 2017
- [j31]Greg Stitt, Robert Karam, Kai Yang, Swarup Bhunia:
A Uniquified Virtualization Approach to Hardware Security. IEEE Embed. Syst. Lett. 9(3): 53-56 (2017) - [j30]David Wilson, Aniruddha Shastri, Greg Stitt:
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Int. J. Reconfigurable Comput. 2017: 5419767:1-5419767:17 (2017) - [j29]Aaron Landy, Greg Stitt:
Serial Arithmetic Strategies for Improving FPGA Throughput. ACM Trans. Embed. Comput. Syst. 16(3): 84:1-84:25 (2017) - [c47]Austin Baylis, Greg Stitt, Ann Gordon-Ross:
Overlay-based side-channel countermeasures: A case study on correlated noise generation. MWSCAS 2017: 1308-1311 - [i2]David Wilson, Greg Stitt:
A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development. CoRR abs/1705.02732 (2017) - 2016
- [j28]David Wilson, Greg Stitt:
The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator. ACM Trans. Reconfigurable Technol. Syst. 9(3): 21:1-21:23 (2016) - [j27]Greg Stitt, Eric Schwartz, Patrick Cooke:
A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 9(3): 23:1-23:22 (2016) - [c46]Aaron Landy, Greg Stitt:
Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining (Abstract Only). FPGA 2016: 282 - [c45]Nalini Kumar, Carlo Pascoe, Christopher Hajas, Herman Lam, Greg Stitt, Alan D. George:
Behavioral Emulation for Scalable Design-Space Exploration of Algorithms and Architectures. ISC Workshops 2016: 5-17 - 2015
- [j26]Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George:
Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs. Int. J. Reconfigurable Comput. 2015: 784672:1-784672:20 (2015) - [j25]Patrick Cooke, Lu Hao, Greg Stitt:
Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability. ACM Trans. Embed. Comput. Syst. 14(3): 54:1-54:25 (2015) - [j24]Patrick Cooke, Jeremy Fowers, Greg Brown, Greg Stitt:
A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window Applications. ACM Trans. Reconfigurable Technol. Syst. 8(1): 2:1-2:24 (2015) - [j23]Robert Kirchgessner, Alan D. George, Greg Stitt:
Low-Overhead FPGA Middleware for Application Portability and Productivity. ACM Trans. Reconfigurable Technol. Syst. 8(4): 21:1-21:22 (2015) - [c44]Dylan Rudolph, Greg Stitt:
An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems. ASAP 2015: 174-180 - [c43]Aniruddha Shastri, Greg Stitt, Eduardo Riccio:
A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications. ASAP 2015: 202-209 - [c42]Aaron Landy, Greg Stitt:
Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs. FCCM 2015: 9-16 - [c41]James Coole, Greg Stitt:
Adjustable-Cost Overlays for Runtime Compilation. FCCM 2015: 21-24 - 2014
- [j22]James Coole, Greg Stitt:
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts. IEEE Micro 34(1): 42-53 (2014) - [c40]Jeremy Fowers, Kalin Ovtcharov, Karin Strauss, Eric S. Chung, Greg Stitt:
A High Memory Bandwidth FPGA Accelerator for Sparse Matrix-Vector Multiplication. FCCM 2014: 36-43 - [c39]Jeremy Fowers, Jianye Liu, Greg Stitt:
A framework for dynamic parallelization of FPGA-accelerated applications. SCOPES 2014: 1-10 - 2013
- [j21]Jeremy Fowers, Greg Brown, John Robert Wernsing, Greg Stitt:
A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors. ACM Trans. Archit. Code Optim. 9(4): 25:1-25:21 (2013) - [c38]Lu Hao, Greg Stitt:
Virtual finite-state-machine architectures for fast compilation and portability. ASAP 2013: 91-94 - [c37]Aaron Landy, Greg Stitt:
Pseudo-constant logic optimization. ASAP 2013: 99-102 - [c36]Patrick Cooke, Jeremy Fowers, Greg Stitt, Lee Hunt:
A comparison of correntropy-based feature tracking on FPGAs and GPUs. ASAP 2013: 237-240 - [c35]Jeremy Fowers, Greg Stitt:
Dynafuse: dynamic dependence analysis for FPGA pipeline fusion and locality optimizations. FPGA 2013: 201-210 - [c34]Patrick Cooke, Jeremy Fowers, Lee Hunt, Greg Stitt:
A high-performance, low-energy FPGA accelerator for correntropy-based feature tracking (abstract only). FPGA 2013: 278 - 2012
- [j20]Lu Hao, Greg Stitt:
Bandwidth-Sensitivity-Aware Arbitration for FPGAs. IEEE Embed. Syst. Lett. 4(3): 73-76 (2012) - [j19]John Robert Wernsing, Greg Stitt:
Elastic computing: A portable optimization framework for hybrid computers. Parallel Comput. 38(8): 438-464 (2012) - [j18]Casey Reardon, Brian Holland, Alan D. George, Greg Stitt, Herman Lam:
RCML: An Environment for Estimation Modeling of Reconfigurable Computing Systems. ACM Trans. Embed. Comput. Syst. 11(S2): 43:1-43:22 (2012) - [j17]Vikas Aggarwal, Greg Stitt, Alan D. George, Changil Yoon:
SCF: A Framework for Task-Level Coordination in Reconfigurable, Heterogeneous Systems. ACM Trans. Reconfigurable Technol. Syst. 5(2): 7:1-7:23 (2012) - [c33]John Robert Wernsing, Greg Stitt, Jeremy Fowers:
The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems. CASES 2012: 81-90 - [c32]Aaron Landy, Greg Stitt:
A low-overhead interconnect architecture for virtual reconfigurable fabrics. CASES 2012: 111-120 - [c31]James Coole, Greg Stitt:
BPR: fast FPGA placement and routing using macroblocks. CODES+ISSS 2012: 275-284 - [c30]John Curreri, Greg Stitt, Alan D. George:
Communication visualization for bottleneck detection of high-level synthesis applications. FPGA 2012: 33-36 - [c29]Jeremy Fowers, Greg Brown, Patrick Cooke, Greg Stitt:
A performance and energy comparison of FPGAs, GPUs, and multicores for sliding-window applications. FPGA 2012: 47-56 - [c28]Robert Kirchgessner, Greg Stitt, Alan D. George, Herman Lam:
VirtualRC: a virtual FPGA platform for applications and tools portability. FPGA 2012: 205-208 - [c27]John Robert Wernsing, Greg Stitt:
RACECAR: a heuristic for automatic function specialization on multi-core heterogeneous systems. PPoPP 2012: 321-322 - 2011
- [j16]Alan D. George, Herman Lam, Greg Stitt:
Novo-G: At the Forefront of Scalable Reconfigurable Supercomputing. Comput. Sci. Eng. 13(1): 82-86 (2011) - [j15]Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole:
An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing. IEEE Des. Test Comput. 28(4): 68-77 (2011) - [j14]Greg Stitt, James Coole:
Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation. IEEE Embed. Syst. Lett. 3(3): 81-84 (2011) - [j13]John Curreri, Greg Stitt, Alan D. George:
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. Int. J. Reconfigurable Comput. 2011: 406857:1-406857:17 (2011) - [j12]Greg Stitt:
Are Field-Programmable Gate Arrays Ready for the Mainstream? IEEE Micro 31(6): 58-63 (2011) - [j11]Greg Stitt, Frank Vahid:
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators. ACM Trans. Design Autom. Electr. Syst. 16(3): 32:1-32:21 (2011) - [j10]Seth Koehler, Greg Stitt, Alan D. George:
Platform-aware bottleneck detection for reconfigurable computing applications. ACM Trans. Reconfigurable Technol. Syst. 4(3): 30:1-30:28 (2011) - 2010
- [j9]James Coole, Greg Stitt:
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures. Int. J. Reconfigurable Comput. 2010: 652620:1-652620:16 (2010) - [c26]James Coole, Greg Stitt:
Intermediate fabrics: virtual architectures for circuit portability and fast placement and routing. CODES+ISSS 2010: 13-22 - [c25]Alan D. George, Herman Lam, Abhijeet Lawande, Carlo Pascoe, Greg Stitt:
Novo-G: A View at the HPC Crossroads for Scientific Computing. ERSA 2010: 21-30 - [c24]Casey Reardon, Alan D. George, Greg Stitt, Herman Lam:
An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems. ERSA 2010: 187-193 - [c23]John Robert Wernsing, Greg Stitt:
A scalable performance prediction heuristic for implementation planning on heterogeneous systems. ESTIMedia 2010: 71-80 - [c22]John Curreri, Greg Stitt, Alan D. George:
High-level synthesis techniques for in-circuit assertion-based verification. IPDPS Workshops 2010: 1-8 - [c21]John Robert Wernsing, Greg Stitt:
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing. LCTES 2010: 115-124 - [c20]Vikas Aggarwal, Changil Yoon, Alan D. George, Herman Lam, Greg Stitt:
Performance modeling for multilevel communication in SHMEM+. PGAS 2010: 7 - [e1]Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt:
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA. CSREA Press 2010, ISBN 1-60132-140-6 [contents]
2000 – 2009
- 2009
- [c19]James Coole, John Robert Wernsing, Greg Stitt:
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. ReConFig 2009: 143-148 - [c18]Vikas Aggarwal, Rafael García, Greg Stitt, Alan D. George, Herman Lam:
SCF: a device- and language-independent task coordination framework for reconfigurable, heterogeneous systems. HPRCTA@SC 2009: 19-28 - [c17]Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George:
A framework for core-level modeling and design of reconfigurable computing algorithms. HPRCTA@SC 2009: 29-38 - [c16]Vikas Aggarwal, Alan D. George, Kishore Yalamanchili, Changil Yoon, Herman Lam, Greg Stitt:
Bridging parallel and reconfigurable computing with multilevel PGAS and SHMEM+. HPRCTA@SC 2009: 47-54 - 2008
- [j8]Frank Vahid, Greg Stitt, Roman L. Lysecky:
Warp Processing: Dynamic Translation of Binaries to FPGA Circuits. Computer 41(7): 40-46 (2008) - [c15]Greg Stitt, Gaurav Chaudhari, James Coole:
Traversal caches: a first step towards FPGA acceleration of pointer-based data structures. CODES+ISSS 2008: 61-66 - [c14]Scott Sirowy, Greg Stitt, Frank Vahid:
C is for circuits: capturing FPGA circuits as sequential code for portability. FPGA 2008: 117-126 - [c13]Greg Stitt, Jason R. Villarreal:
Recursion flattening. ACM Great Lakes Symposium on VLSI 2008: 131-134 - [c12]Greg Stitt:
Hardware/software partitioning with multi-version implementation exploration. ACM Great Lakes Symposium on VLSI 2008: 143-146 - 2007
- [j7]Greg Stitt, Frank Vahid:
Binary synthesis. ACM Trans. Design Autom. Electr. Syst. 12(3): 34:1-34:30 (2007) - [c11]Greg Stitt, Frank Vahid:
Thread warping: a framework for dynamic synthesis of thread accelerators. CODES+ISSS 2007: 93-98 - [i1]Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. CoRR abs/0710.4700 (2007) - 2006
- [j6]Roman L. Lysecky, Greg Stitt, Frank Vahid:
Warp Processors. ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006) - [c10]Greg Stitt, Frank Vahid, Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C. ICCAD 2006: 716-723 - 2005
- [c9]Greg Stitt, Frank Vahid, Gordon McGregor, Brian Einloth:
Hardware/software partitioning of software binaries: a case study of H.264 decode. CODES+ISSS 2005: 285-290 - [c8]Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. DATE 2005: 396-397 - [c7]Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure. FPGA 2005: 118-124 - 2004
- [j5]Greg Stitt, Frank Vahid, Shawn Nematbakhsh:
Energy savings and speedups from partitioning critical software loops to hardware in embedded systems. ACM Trans. Embed. Comput. Syst. 3(1): 218-232 (2004) - 2003
- [j4]Frank Vahid, Roman L. Lysecky, Chuanjun Zhang, Greg Stitt:
Highly configurable platforms for embedded computing systems. Microelectron. J. 34(11): 1025-1029 (2003) - [c6]Greg Stitt, Roman L. Lysecky, Frank Vahid:
Dynamic hardware/software partitioning: a first approach. DAC 2003: 250-255 - [c5]Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt:
Profiling tools for hardware/software partitioning of embedded applications. LCTES 2003: 189-198 - 2002
- [j3]Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar:
Improving Software Performance with Configurable Logic. Des. Autom. Embed. Syst. 7(4): 325-339 (2002) - [j2]Greg Stitt, Frank Vahid:
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Des. Test Comput. 19(6): 36-43 (2002) - [c4]Brian Grattan, Greg Stitt, Frank Vahid:
Codesign-extended applications. CODES 2002: 1-6 - [c3]Greg Stitt, Brian Grattan, Jason R. Villarreal, Frank Vahid:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy. FCCM 2002: 143-151 - [c2]Greg Stitt, Frank Vahid:
Hardware/software partitioning of software binaries. ICCAD 2002: 164-170 - 2001
- [j1]Frank Vahid, Rilesh Patel, Greg Stitt:
Propagating constants past software to hardware peripherals in fixed-application embedded systems. SIGARCH Comput. Archit. News 29(5): 25-30 (2001) - 2000
- [c1]Greg Stitt, Frank Vahid, Tony Givargis, Roman L. Lysecky:
A first-step towards an architecture tuning methodology for low power. CASES 2000: 187-192
Coauthor Index
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last updated on 2024-05-08 20:59 CEST by the dblp team
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