iBet uBet web content aggregator. Adding the entire web to your favor.

Link to original content: https://dblp.org/pid/10/6485.rss

dblp: Stefan Rusu https://dblp.org/pid/10/6485.html dblp person page RSS feed Thu, 25 Apr 2024 05:35:05 +0200 en-US daily 1 released under the CC0 1.0 license dblp@dagstuhl.de (dblp team) dblp@dagstuhl.de (dblp team) Computers/Computer_Science/Publications/Bibliographies http://www.rssboard.org/rss-specification https://dblp.org/img/logo.144x51.pngdblp: Stefan Rusuhttps://dblp.org/pid/10/6485.html14451 A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing.https://doi.org/10.1109/JSSC.2019.2960207Mu-Shan Lin

, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu

, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong

, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. IEEE J. Solid State Circuits 55(4): 956-966 (2020)]]>https://dblp.org/rec/journals/jssc/LinHTTHCHHCGFRL20Wed, 01 Jan 2020 00:00:00 +0100 Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC).https://doi.org/10.1109/JSSC.2019.2919403Ángel Rodríguez-Vázquez, Kaushik Sengupta

, Stefan Rusu:
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 54(7): 1827-1829 (2019)]]>https://dblp.org/rec/journals/jssc/Rodriguez-Vazquez19Tue, 01 Jan 2019 00:00:00 +0100 Hot Chips 30.https://doi.org/10.1109/MM.2019.2899510John Kubiatowicz, Stefan Rusu:
Hot Chips 30. IEEE Micro 39(2): 6-8 (2019)]]>https://dblp.org/rec/journals/micro/KubiatowiczR19Tue, 01 Jan 2019 00:00:00 +0100 A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing.https://doi.org/10.23919/VLSIC.2019.8778161Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Tom Chen, Wen-Hung Huang, Jack Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7nm 4GHz Arm^®-core-based CoWoS^® Chiplet Design for High Performance Computing. VLSI Circuits 2019: 28-]]>https://dblp.org/rec/conf/vlsic/LinHTTHCHHCGFRL19Tue, 01 Jan 2019 00:00:00 +0100 Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC).https://doi.org/10.1109/JSSC.2016.2565266Andrea Mazzanti, Bram Nauta

, Stefan Rusu:
Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 51(7): 1511-1513 (2016)]]>https://dblp.org/rec/journals/jssc/MazzantiNR16Fri, 01 Jan 2016 00:00:00 +0100 Welcome to 2016 Hot Chips.https://doi.org/10.1109/HOTCHIPS.2016.7936200Stefan Rusu:
Welcome to 2016 Hot Chips. Hot Chips Symposium 2016: 1-10]]>https://dblp.org/rec/conf/hotchips/Rusu16Fri, 01 Jan 2016 00:00:00 +0100 A 22 nm 15-Core Enterprise Xeon® Processor Family.https://doi.org/10.1109/JSSC.2014.2368933Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li

, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits 50(1): 35-48 (2015)]]>https://dblp.org/rec/journals/jssc/RusuMATCMLVVW15Thu, 01 Jan 2015 00:00:00 +0100 Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).https://doi.org/10.1109/JSSC.2015.2481659Stefan Rusu, Gregory Chen:
Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 50(11): 2472-2474 (2015)]]>https://dblp.org/rec/journals/jssc/RusuC15Thu, 01 Jan 2015 00:00:00 +0100 Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC).https://doi.org/10.1109/JSSC.2014.2331082Yann Deval

, Stefan Rusu:
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 49(7): 1460-1462 (2014)]]>https://dblp.org/rec/journals/jssc/DevalR14Wed, 01 Jan 2014 00:00:00 +0100 5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family.https://doi.org/10.1109/ISSCC.2014.6757356Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li

, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC 2014: 102-103]]>https://dblp.org/rec/conf/isscc/RusuMATCMLVVW14Wed, 01 Jan 2014 00:00:00 +0100 A 45 nm 8-Core Enterprise Xeon¯ Processor.https://doi.org/10.1109/JSSC.2009.2034076Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010)]]>https://dblp.org/rec/journals/jssc/RusuTMSACVRKV10Fri, 01 Jan 2010 00:00:00 +0100 Introduction to the Special Issue on the 34th ESSCIRC.https://doi.org/10.1109/JSSC.2009.2021436Kari A. I. Halonen, Kofi A. A. Makinwa, Stefan Rusu:
Introduction to the Special Issue on the 34th ESSCIRC. IEEE J. Solid State Circuits 44(7): 1859-1861 (2009)]]>https://dblp.org/rec/journals/jssc/HalonenMR09Thu, 01 Jan 2009 00:00:00 +0100 Power reduction techniques for an 8-core xeon® processor.https://doi.org/10.1109/ESSCIRC.2009.5326028Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343]]>https://dblp.org/rec/conf/esscirc/RusuTMSACVRKV09Thu, 01 Jan 2009 00:00:00 +0100 A 45nm 8-core enterprise Xeon® processor.https://doi.org/10.1109/ISSCC.2009.4977305Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. ISSCC 2009: 56-57]]>https://dblp.org/rec/conf/isscc/RusuTMSACVRK09Thu, 01 Jan 2009 00:00:00 +0100 Multi-domain processors.https://doi.org/10.1109/ISSCC.2009.4977534Stefan Rusu:
Multi-domain processors. ISSCC 2009: 509]]>https://dblp.org/rec/conf/isscc/Rusu09Thu, 01 Jan 2009 00:00:00 +0100 Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007).https://doi.org/10.1109/JSSC.2008.922406Andrea Baschirotto

, Edoardo Charbon, Stefan Rusu:
Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007). IEEE J. Solid State Circuits 43(7): 1507-1510 (2008)]]>https://dblp.org/rec/journals/jssc/BaschirottoCR08Tue, 01 Jan 2008 00:00:00 +0100 Short Course.https://doi.org/10.1109/ISSCC.2008.4523324Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders:
Short Course. ISSCC 2008: 648-649]]>https://dblp.org/rec/conf/isscc/GaltonAIRS08Tue, 01 Jan 2008 00:00:00 +0100 A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.https://doi.org/10.1109/JSSC.2006.885041Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007)]]>https://dblp.org/rec/journals/jssc/RusuTMACCSBVLLV07Mon, 01 Jan 2007 00:00:00 +0100 The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series.https://doi.org/10.1109/JSSC.2007.892185Jonathan Chang, Ming Huang, Jonathan Shoemaker, John Benoit, Szu-Liang Chen, Wei Chen, Siufu Chiu, Raghuraman Ganesan, Gloria Leong, Venkata Lukka, Stefan Rusu, Durgesh Srivastava:
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. IEEE J. Solid State Circuits 42(4): 846-852 (2007)]]>https://dblp.org/rec/journals/jssc/ChangHSBCCCGLLR07Mon, 01 Jan 2007 00:00:00 +0100 Introduction to the Special Issue on ESSCIRC 2006.https://doi.org/10.1109/JSSC.2007.899123Andreas Kaiser

, Stefan Rusu:
Introduction to the Special Issue on ESSCIRC 2006. IEEE J. Solid State Circuits 42(7): 1453-1454 (2007)]]>https://dblp.org/rec/journals/jssc/KaiserR07Mon, 01 Jan 2007 00:00:00 +0100 Microprocessors.https://doi.org/10.1109/ISSCC.2007.373604Stefan Rusu, Jim Warnock:
Microprocessors. ISSCC 2007: 94-95]]>https://dblp.org/rec/conf/isscc/RusuW07Mon, 01 Jan 2007 00:00:00 +0100 A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache.https://doi.org/10.1109/ISSCC.2006.1696062Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang:
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC 2006: 315-324]]>https://dblp.org/rec/conf/isscc/RusuTMAC06Sun, 01 Jan 2006 00:00:00 +0100 A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor.https://doi.org/10.1109/JSSC.2004.837970Jonathan Chang, Stefan Rusu, Jonathan Shoemaker, Simon Tam, Ming Huang, Mizan Haque, Siufu Chiu, Kevin Truong, Mesbah Karim, Gloria Leong, Kiran Desai, Richard Goe, Sandhya Kulkarni:
A 130-nm triple-V_t 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. IEEE J. Solid State Circuits 40(1): 195-203 (2005)]]>https://dblp.org/rec/journals/jssc/ChangRSTHHCTKLD05Sat, 01 Jan 2005 00:00:00 +0100 Introduction to the Special Issue on ESSCIRC'2004.https://doi.org/10.1109/JSSC.2005.846446Rolf Koch, Stefan Rusu:
Introduction to the Special Issue on ESSCIRC'2004. IEEE J. Solid State Circuits 40(7): 1403-1405 (2005)]]>https://dblp.org/rec/journals/jssc/KochR05Sat, 01 Jan 2005 00:00:00 +0100 Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.https://doi.org/10.1109/MM.2004.1289279Stefan Rusu, Harry Muljono, Brian S. Cherkauer:
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. IEEE Micro 24(2): 10-18 (2004)]]>https://dblp.org/rec/journals/micro/RusuMC04Thu, 01 Jan 2004 00:00:00 +0100 Clock generation and distribution in high-performance processors.https://doi.org/10.1109/ISSOC.2004.1411188Stefan Rusu:
Clock generation and distribution in high-performance processors. SoC 2004]]>https://dblp.org/rec/conf/issoc/Rusu04Thu, 01 Jan 2004 00:00:00 +0100 A 400-MT/s 6.4-GB/s multiprocessor bus interface.https://doi.org/10.1109/JSSC.2003.818295Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu:
A 400-MT/s 6.4-GB/s multiprocessor bus interface. IEEE J. Solid State Circuits 38(11): 1846-1856 (2003)]]>https://dblp.org/rec/journals/jssc/MuljonoLTWAHAR03Wed, 01 Jan 2003 00:00:00 +0100 A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.https://doi.org/10.1109/JSSC.2003.818293Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer:
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 38(11): 1887-1895 (2003)]]>https://dblp.org/rec/journals/jssc/RusuSTLMC03Wed, 01 Jan 2003 00:00:00 +0100 A 1.5GHz third generation itanium® 2 processor.https://doi.org/10.1145/775832.776011Jason Stinson, Stefan Rusu:
A 1.5GHz third generation itanium® 2 processor. DAC 2003: 706-709]]>https://dblp.org/rec/conf/dac/StinsonR03Wed, 01 Jan 2003 00:00:00 +0100 Guest editorial.https://doi.org/10.1109/JSSC.2002.1015675Christian C. Enz, Stefan Rusu:
Guest editorial. IEEE J. Solid State Circuits 37(7): 795-797 (2002)]]>https://dblp.org/rec/journals/jssc/EnzR02Tue, 01 Jan 2002 00:00:00 +0100 Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract).https://doi.org/10.1109/ASPDAC.2002.994875Stefan Rusu, Manoj Sachdev, Christer Svensson, Bram Nauta:
Trends and Challenges in VLSI Technology Scaling towards 100nm (Tutorial Abstract). ASP-DAC/VLSI Design 2002: 16-17]]>https://dblp.org/rec/conf/vlsid/RusuSSN02Tue, 01 Jan 2002 00:00:00 +0100 The first IA-64 microprocessor.https://doi.org/10.1109/4.881197Stefan Rusu, Gadi Singer:
The first IA-64 microprocessor. IEEE J. Solid State Circuits 35(11): 1539-1544 (2000)]]>https://dblp.org/rec/journals/jssc/RusuS00Sat, 01 Jan 2000 00:00:00 +0100 Clock generation and distribution for the first IA-64 microprocessor.https://doi.org/10.1109/4.881198Simon Tam, Stefan Rusu, Utpal Nagarji Desai, Robert Kim, Ji Zhang, Ian Young:
Clock generation and distribution for the first IA-64 microprocessor. IEEE J. Solid State Circuits 35(11): 1545-1552 (2000)]]>https://dblp.org/rec/journals/jssc/TamRDKZY00Sat, 01 Jan 2000 00:00:00 +0100 Itanium processor clock design.https://doi.org/10.1145/332357.332380Utpal Desai, Simon M. Tam, Robert Kim, Ji Zhang, Stefan Rusu:
Itanium processor clock design. ISPD 2000: 94-98]]>https://dblp.org/rec/conf/ispd/DesaiTKZR00Sat, 01 Jan 2000 00:00:00 +0100 TONIC: A timing database for VLSI design.https://doi.org/10.1109/EURDAC.1993.410672Gregory Schulte, Peter Tong, Stefan Rusu, Stuart Taylor:
TONIC: A timing database for VLSI design. EURO-DAC 1993: 426-431]]>https://dblp.org/rec/conf/eurodac/SchulteTRT93Fri, 01 Jan 1993 00:00:00 +0100