Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
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TY - JOUR
ID - DBLP:journals/jssc/NakagomeG04
AU - Nakagome, Yoshinobu
AU - Gieseke, Bruce
TI - Introduction to the Special Issue.
JO - IEEE J. Solid State Circuits
VL - 39
IS - 4
SP - 547
EP - 548
PY - 2004//
DO - 10.1109/JSSC.2004.824701
UR - https://doi.org/10.1109/JSSC.2004.824701
ER -
TY - JOUR
ID - DBLP:journals/ibmrd/NakagomeHKI03
AU - Nakagome, Yoshinobu
AU - Horiguchi, Masashi
AU - Kawahara, Takayuki
AU - Itoh, Kiyoo
TI - Review and future prospects of low-voltage RAM circuits.
JO - IBM J. Res. Dev.
VL - 47
IS - 5-6
SP - 525
EP - 552
PY - 2003//
DO - 10.1147/RD.475.0525
UR - https://doi.org/10.1147/rd.475.0525
ER -
TY - JOUR
ID - DBLP:journals/jssc/BorkarN03
AU - Borkar, Shekhar
AU - Nakagome, Yoshinobu
TI - Guest Editorial.
JO - IEEE J. Solid State Circuits
VL - 38
IS - 5
SP - 687
PY - 2003//
DO - 10.1109/JSSC.2003.810028
UR - https://doi.org/10.1109/JSSC.2003.810028
ER -
TY - JOUR
ID - DBLP:journals/jssc/SatoNSN99
AU - Sato, Takashi
AU - Nishio, Yoji
AU - Sugano, Toshio
AU - Nakagome, Yoshinobu
TI - A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM.
JO - IEEE J. Solid State Circuits
VL - 34
IS - 5
SP - 653
EP - 660
PY - 1999//
DO - 10.1109/4.760375
UR - https://doi.org/10.1109/4.760375
ER -
TY - JOUR
ID - DBLP:journals/jssc/ItohNKW97
AU - Itoh, Kiyoo
AU - Nakagome, Yoshinobu
AU - Kimura, Shin'ichiro
AU - Watanabe, Takao
TI - Limitations and challenges of multigigabit DRAM chip design.
JO - IEEE J. Solid State Circuits
VL - 32
IS - 5
SP - 624
EP - 634
PY - 1997//
DO - 10.1109/4.568820
UR - https://doi.org/10.1109/4.568820
ER -
TY - JOUR
ID - DBLP:journals/jssc/WatanabeFYTASTS97
AU - Watanabe, Takao
AU - Fujita, Ryo
AU - Yanagisawa, Kazumasa
AU - Tanaka, Hitoshi
AU - Ayukawa, Kazushige
AU - Soga, Mitsuru
AU - Tanaka, Yuji
AU - Sugie, Yoshimitsu
AU - Nakagome, Yoshinobu
TI - A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip.
JO - IEEE J. Solid State Circuits
VL - 32
IS - 5
SP - 635
EP - 641
PY - 1997//
DO - 10.1109/4.568823
UR - https://doi.org/10.1109/4.568823
ER -
TY - JOUR
ID - DBLP:journals/jssc/OhkuboSSYSSN95
AU - Ohkubo, Norio
AU - Suzuki, Makoto
AU - Shinbo, Toshinobu
AU - Yamanaka, Toshiaki
AU - Shimizu, Akihiro
AU - Sasaki, Katsuro
AU - Nakagome, Yoshinobu
TI - A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
JO - IEEE J. Solid State Circuits
VL - 30
IS - 3
SP - 251
EP - 257
PY - 1995/03/
DO - 10.1109/4.364439
UR - https://doi.org/10.1109/4.364439
ER -
TY - JOUR
ID - DBLP:journals/jssc/TachibanaHTSYN95
AU - Tachibana, Suguru
AU - Higuchi, Hisayuki
AU - Takasugi, Koichi
AU - Sasaki, Katsuro
AU - Yamanaka, Toshiaki
AU - Nakagome, Yoshinobu
TI - A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.
JO - IEEE J. Solid State Circuits
VL - 30
IS - 4
SP - 487
EP - 490
PY - 1995/04/
DO - 10.1109/4.375970
UR - https://doi.org/10.1109/4.375970
ER -
TY - JOUR
ID - DBLP:journals/jssc/SakataHSUTYNAKONMTIYGSKYNT95
AU - Sakata, Takeshi
AU - Horiguchi, Masashi
AU - Sekiguchi, Tomonori
AU - Ueda, Shigeki
AU - Tanaka, Hitoshi
AU - Yamasaki, Eiji
AU - Nakagome, Yoshinobu
AU - Aoki, Masakazu
AU - Kaga, Toru
AU - Ohkura, Makoto
AU - Nagai, Ryo
AU - Murai, Fumio
AU - Tanaka, Toshihiko
AU - Iijima, Shimpei
AU - Yokoyama, Natsuki
AU - Gotoh, Yasushi
AU - Shoji, Ken'ichi
AU - Kisu, Teruaki
AU - Yamashita, Hisaomi
AU - Nishida, Takashi
AU - Takeda, Eiji
TI - An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.
JO - IEEE J. Solid State Circuits
VL - 30
IS - 11
SP - 1165
EP - 1173
PY - 1995/11/
DO - 10.1109/4.475703
UR - https://doi.org/10.1109/4.475703
ER -
TY - JOUR
ID - DBLP:journals/jssc/SekiguchiHSNUA95
AU - Sekiguchi, Tomonori
AU - Horiguchi, Masashi
AU - Sakata, Takeshi
AU - Nakagome, Yoshinobu
AU - Ueda, Shigeki
AU - Aoki, Masakazu
TI - Low-noise, high-speed data transmission using a ringing-canceling output buffer.
JO - IEEE J. Solid State Circuits
VL - 30
IS - 12
SP - 1569
EP - 1574
PY - 1995/12/
DO - 10.1109/4.482208
UR - https://doi.org/10.1109/4.482208
ER -
TY - JOUR
ID - DBLP:journals/pieee/ItohSN95
AU - Itoh, Kiyoo
AU - Sasaki, Katsuro
AU - Nakagome, Yoshinobu
TI - Trends in low-power RAM circuit technologies.
JO - Proc. IEEE
VL - 83
IS - 4
SP - 524
EP - 543
PY - 1995//
DO - 10.1109/5.371965
UR - https://doi.org/10.1109/5.371965
ER -
TY - JOUR
ID - DBLP:journals/jssc/TanakaNEYAM94
AU - Tanaka, Hitoshi
AU - Nakagome, Yoshinobu
AU - Etoh, Jun
AU - Yamasaki, Eiji
AU - Aoki, Masakazu
AU - Miyazawa, Kazuyuki
TI - Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs.
JO - IEEE J. Solid State Circuits
VL - 29
IS - 4
SP - 448
EP - 453
PY - 1994/04/
DO - 10.1109/4.280694
UR - https://doi.org/10.1109/4.280694
ER -
TY - JOUR
ID - DBLP:journals/jssc/AokiINHKKI89
AU - Aoki, Masakazu
AU - Ikenaga, Shin'ichi
AU - Nakagome, Yoshinobu
AU - Horiguchi, Masashi
AU - Kawase, Yasushi
AU - Kawamoto, Yoshifumi
AU - Itoh, Kiyoo
TI - New DRAM noise generation under half-V