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Mehdi Sedighi
Eesa Nikahd Morteza Saheb Zamani Mehdi Sedighi Low-overhead code concatenation approaches for universal quantum computation. 73 2023 January 22 Quantum Inf. Process. 1 https://doi.org/10.1007/s11128-023-03829-1 db/journals/qip/qip22.html#NikahdZS23
Mohammad Hadi Mottaghi Mehdi Sedighi Morteza Saheb Zamani FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. 2277-2286 2022 71 IEEE Trans. Computers 9 https://doi.org/10.1109/TC.2021.3127082 db/journals/tc/tc71.html#MottaghiSZ22
Amir Bavafa Toosi Mehdi Sedighi FERMAT: FPGA energy reduction method by approximation theory. 9721-9745 2021 77 J. Supercomput. 9 https://doi.org/10.1007/s11227-021-03644-4 db/journals/tjs/tjs77.html#ToosiS21
Mona Arabzadeh Mehdi Sedighi Morteza Saheb Zamani Sayed-Amir Marashi A system architecture for parallel analysis of flux-balanced metabolic pathways. 107309 2020 88 Comput. Biol. Chem. https://doi.org/10.1016/j.compbiolchem.2020.107309 https://www.wikidata.org/entity/Q97517068 db/journals/candc/candc88.html#ArabzadehSZM20
Mohammad Hadi Mottaghi Mehdi Sedighi Morteza Saheb Zamani Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. 833-844 2020 69 IEEE Trans. Reliab. 2 https://doi.org/10.1109/TR.2019.2897591 db/journals/tr/tr69.html#MottaghiSZ20
Mona Arabzadeh Morteza Saheb Zamani Mehdi Sedighi Sayed-Amir Marashi A graph-based approach to analyze flux-balanced pathways in metabolic networks. 40-51 2018 165 Biosyst. https://doi.org/10.1016/j.biosystems.2017.12.001 https://www.wikidata.org/entity/Q50033744 db/journals/biosystems/biosystems165.html#ArabzadehZSM18
Samaneh Emami Mehdi Sedighi An optimized reconfigurable architecture for hardware implementation of decimal arithmetic. 18-29 2017 63 Comput. Electr. Eng. https://doi.org/10.1016/j.compeleceng.2017.08.018 db/journals/cee/cee63.html#EmamiS17
Behrouz Zolfaghari Mehran S. Fallah Mehdi Sedighi S-Restricted Compositions Revisited. 2017 19 Discret. Math. Theor. Comput. Sci. 1 https://doi.org/10.23638/DMTCS-19-1-9 db/journals/dmtcs/dmtcs19.html#ZolfaghariFS17
Mahboobeh Houshmand Mehdi Sedighi Morteza Saheb Zamani Kourosh Marjoei Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. 55:1-55:27 2017 13 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/3064834 db/journals/jetc/jetc13.html#HoushmandSZM17
Maryam Eslamy Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. 2017 abs/1704.07378 CoRR http://arxiv.org/abs/1704.07378 db/journals/corr/corr1704.html#EslamyHZS17
Mona Arabzadeh Mahboobeh Houshmand Mehdi Sedighi Morteza Saheb Zamani Quantum-Logic Synthesis of Hermitian Gates. 40:1-40:15 2016 12 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/2794263 db/journals/jetc/jetc12.html#ArabzadehHSZ16
Mohammad Reza Bagheri Reza Gholami Sohrab Mortazavi Ghalati Mehdi Sedighi Location-based scheduling: An approach to address challenges of Big Data and Mobile Cloud Computing. 700-706 2016 IST https://doi.org/10.1109/ISTEL.2016.7881913 conf/istel/2016 db/conf/istel/istel2016.html#BagheriGGS16
Eesa Nikahd Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi One-Way Quantum Computer Simulation. 2016 abs/1604.05659 CoRR http://arxiv.org/abs/1604.05659 db/journals/corr/corr1604.html#NikahdHZS16
Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi Monireh Houshmand GA-based approach to find the stabilizers of a given sub-space. 57-71 2015 16 Genet. Program. Evolvable Mach. 1 https://doi.org/10.1007/s10710-014-9219-z db/journals/gpem/gpem16.html#HoushmandZSH15
Eesa Nikahd Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi One-way quantum computer simulation. 210-222 2015 39 Microprocess. Microsystems 3 https://doi.org/10.1016/j.micpro.2015.02.007 db/journals/mam/mam39.html#NikahdHZS15
Mehdi Sedighi Foroogh Haddadi Samaneh Emami Mahya Saffarpour A heuristic algorithm for high level synthesis of decimal arithmetic circuits using SystemC. 1-6 2015 DTIS https://doi.org/10.1109/DTIS.2015.7127374 conf/dtis/2015 db/conf/dtis/dtis2015.html#SedighiHES15
Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi Mona Arabzadeh Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. 28:1-28:10 2014 11 ACM J. Emerg. Technol. Comput. Syst. 3 https://doi.org/10.1145/2629526 db/journals/jetc/jetc11.html#HoushmandZSA14
Naser MohammadZadeh Morteza Saheb Zamani Mehdi Sedighi Quantum circuit physical design methodology with emphasis on physical synthesis. 445-465 2014 13 Quantum Inf. Process. 2 https://doi.org/10.1007/s11128-013-0661-2 db/journals/qip/qip13.html#MohammadZadehZS14
Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi Mohammad Hossein Samavatian Automatic translation of quantum circuits to optimized one-way quantum computation patterns. 2463-2482 2014 13 Quantum Inf. Process. 11 https://doi.org/10.1007/s11128-014-0801-3 db/journals/qip/qip13.html#HoushmandZSS14
Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi Mona Arabzadeh Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. 2014 abs/1405.6741 CoRR http://arxiv.org/abs/1405.6741 db/journals/corr/corr1405.html#HoushmandZSA14
Mona Arabzadeh Morteza Saheb Zamani Mehdi Sedighi Mehdi Saeedi Depth-optimized reversible circuit synthesis. 1677-1699 2013 12 Quantum Inf. Process. 4 https://doi.org/10.1007/s11128-012-0482-8 db/journals/qip/qip12.html#ArabzadehZSS13
Maryam Yazdani Morteza Saheb Zamani Mehdi Sedighi A quantum physical design flow using ILP and graph drawing. 3239-3264 2013 12 Quantum Inf. Process. 10 https://doi.org/10.1007/s11128-013-0597-6 db/journals/qip/qip12.html#YazdaniZS13
Maryam Yazdani Morteza Saheb Zamani Mehdi Sedighi A Quantum Physical Design Flow Using ILP and Graph Drawing. 2013 CoRR http://arxiv.org/abs/1306.2037 abs/1306.2037 db/journals/corr/corr1306.html#YazdaniZS13
Eesa Nikahd Mahboobeh Houshmand Morteza Saheb Zamani Mehdi Sedighi OWQS: One-Way Quantum Computation Simulator. 98-104 2012 DSD https://doi.org/10.1109/DSD.2012.100 https://doi.ieeecomputersociety.org/10.1109/DSD.2012.100 conf/dsd/2012 db/conf/dsd/dsd2012.html#NikahdHZS12 Mehdi Harounabadi Mehdi Sedighi A fast response dynamic bandwidth allocation algorithm for a converged EPON and WiMAX network. 470-476 2012 IST https://doi.org/10.1109/ISTEL.2012.6483035 conf/istel/2012 db/conf/istel/istel2012.html#HarounabadiS12
Mona Arabzadeh Morteza Saheb Zamani Mehdi Sedighi Mehdi Saeedi Depth-Optimized Reversible Circuit Synthesis. 2012 abs/1208.5425 CoRR http://arxiv.org/abs/1208.5425 db/journals/corr/corr1208.html#ArabzadehZSS12
Hamid Hassanpour Mehdi Sedighi Ali Reza Manashty Video Frame's Background Modeling: Reviewing the Techniques. 72-78 2011 2 J. Signal Inf. Process. 2 https://doi.org/10.4236/jsip.2011.22010 db/journals/jsip/jsip2.html#HassanpourSM11
Mehdi Saeedi Mona Arabzadeh Morteza Saheb Zamani Mehdi Sedighi Block-based quantum-logic synthesis. 262-277 2011 11 Quantum Inf. Comput. 3&4 https://doi.org/10.26421/QIC11.3-4-6 db/journals/qic/qic11.html#SaeediAZS11
Naser MohammadZadeh Morteza Saheb Zamani Mehdi Sedighi Auxiliary qubit selection: a physical synthesis technique for quantum circuits. 139-154 2011 10 Quantum Inf. Process. 2 https://doi.org/10.1007/s11128-010-0183-0 db/journals/qip/qip10.html#MohammadZadehZS11
Mehdi Sedighi Sam Farrokhi GALS system optimization using retiming concept. 209-215 2010 7 IEICE Electron. Express 3 https://doi.org/10.1587/elex.7.209 db/journals/ieiceee/ieiceee7.html#SedighiF10
Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi Zahra Sasanian Reversible circuit synthesis using a cycle-based approach. 13:1-13:26 2010 6 ACM J. Emerg. Technol. Comput. Syst. 4 https://doi.org/10.1145/1877745.1877747 db/journals/jetc/jetc6.html#SaeediZSS10
Mehdi Saeedi Mehdi Sedighi Morteza Saheb Zamani A library-based synthesis methodology for reversible logic. 185-194 2010 41 Microelectron. J. 4 https://doi.org/10.1016/j.mejo.2010.02.002 db/journals/mj/mj41.html#SaeediSZ10
Naser MohammadZadeh Mehdi Sedighi Morteza Saheb Zamani Quantum physical synthesis: Improving physical design by netlist modifications. 219-230 2010 41 Microelectron. J. 4 https://doi.org/10.1016/j.mejo.2010.02.005 db/journals/mj/mj41.html#MohammadZadehSZ10
Mehdi Saeedi Mehdi Sedighi Morteza Saheb Zamani A Library-Based Synthesis Methodology for Reversible Logic. 2010 abs/1004.1697 CoRR http://arxiv.org/abs/1004.1697 db/journals/corr/corr1004.html#SaeediSZ10
Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi Zahra Sasanian Reversible Circuit Synthesis Using a Cycle-Based Approach. 2010 abs/1004.4320 CoRR http://arxiv.org/abs/1004.4320 db/journals/corr/corr1004.html#SaeediZSS10
Mehdi Saeedi Mona Arabzadeh Morteza Saheb Zamani Mehdi Sedighi Block-based quantum-logic synthesis. 2010 abs/1011.2159 CoRR http://arxiv.org/abs/1011.2159 db/journals/corr/corr1011.html#SaeediAZS10
Zahra Sasanian Mehdi Saeedi Mehdi Sedighi Morteza Saheb Zamani A cycle-based synthesis algorithm for reversible logic. 745-750 2009 ASP-DAC https://doi.org/10.1109/ASPDAC.2009.4796569 http://dl.acm.org/citation.cfm?id=1509801 conf/aspdac/2009 db/conf/aspdac/aspdac2009.html#SasanianSSZ09 Naser MohammadZadeh Morteza Saheb Zamani Mehdi Sedighi Improving Latency of Quantum Circuits by Gate Exchanging. 67-73 2009 DSD https://doi.org/10.1109/DSD.2009.191 https://doi.ieeecomputersociety.org/10.1109/DSD.2009.191 conf/dsd/2009 db/conf/dsd/dsd2009.html#MohammadZadehZS09
Mehdi Saeedi Mehdi Sedighi Morteza Saheb Zamani Synthesis of reversible circuits using a moving forward strategy. 638-643 2008 5 IEICE Electron. Express 17 https://doi.org/10.1587/elex.5.638 db/journals/ieiceee/ieiceee5.html#SaeediSZ08
Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. 83-88 2008 ASP-DAC https://doi.org/10.1109/ASPDAC.2008.4484066 http://dl.acm.org/citation.cfm?id=1356822 conf/aspdac/2008 db/conf/aspdac/aspdac2008.html#SaeediZS08 Mehdi Saeedi Naser MohammadZadeh Mehdi Sedighi Morteza Saheb Zamani Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. 490-493 2008 DSD https://doi.org/10.1109/DSD.2008.70 https://doi.ieeecomputersociety.org/10.1109/DSD.2008.70 conf/dsd/2008 db/conf/dsd/dsd2008.html#SaeediMSZ08 Ehsan K. Ardestani Morteza Saheb Zamani Mehdi Sedighi A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. 803-806 2008 DSD https://doi.org/10.1109/DSD.2008.95 https://doi.ieeecomputersociety.org/10.1109/DSD.2008.95 conf/dsd/2008 db/conf/dsd/dsd2008.html#ArdestaniZS08 Mahdi Aminian Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi FPGA-Based Circuit Model Emulation of Quantum Algorithms. 399-404 2008 ISVLSI https://doi.org/10.1109/ISVLSI.2008.43 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2008.43 conf/isvlsi/2008 db/conf/isvlsi/isvlsi2008.html#AminianSZS08 Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. 339-346 2007 DSD https://doi.org/10.1109/DSD.2007.4341490 conf/dsd/2007 db/conf/dsd/dsd2007.html#SaeediZS07 Mehdi Saeedi Mehdi Sedighi Morteza Saheb Zamani A novel synthesis algorithm for reversible circuits. 65-68 2007 conf/iccad/2007 ICCAD https://doi.org/10.1109/ICCAD.2007.4397245 https://doi.ieeecomputersociety.org/10.1109/ICCAD.2007.4397245 https://dl.acm.org/citation.cfm?id=1326088 db/conf/iccad/iccad2007.html#SaeediSZ07 Mehdi Saeedi Morteza Saheb Zamani Mehdi Sedighi On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. 428-436 2007 conf/isvlsi/2007 ISVLSI https://doi.org/10.1109/ISVLSI.2007.72 https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.72 db/conf/isvlsi/isvlsi2007.html#SaeediZS07
Farhad Mehdipour Morteza Saheb Zamani Mehdi Sedighi An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. 52-62 2006 30 Microprocess. Microsystems 1 https://doi.org/10.1016/j.micpro.2005.03.002 db/journals/mam/mam30.html#MehdipourZS06
Farhad Mehdipour Hamid Noori Morteza Saheb Zamani Kazuaki J. Murakami Mehdi Sedighi Koji Inoue An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. 219-230 2006 conf/aPcsac/2006 Asia-Pacific Computer Systems Architecture Conference https://doi.org/10.1007/11859802_18 db/conf/aPcsac/aPcsac2006.html#MehdipourNZMSI06 Farhad Mehdipour Morteza Saheb Zamani Mehdi Sedighi Kazuaki J. Murakami Hamid Noori GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. 227-230 2006 conf/ersa/2006 ERSA db/conf/ersa/ersa2006.html#MehdipourZSMN06 Farhad Mehdipour Hamid Noori Morteza Saheb Zamani Kazuaki J. Murakami Koji Inoue Mehdi Sedighi Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. 722-731 2006 conf/euc/2006 EUC https://doi.org/10.1007/11802167_73 db/conf/euc/euc2006.html#MehdipourNZMIS06 M. Rahmaniheris Mehdi Sedighi A New Algorithm for Resource Manager to Enhance the Quality of Service in VoIP Systems. 2 2006 conf/icn/2006 ICN/ICONS/MCL https://doi.org/10.1109/ICNICONSMCL.2006.19 https://doi.ieeecomputersociety.org/10.1109/ICNICONSMCL.2006.19 db/conf/icn/icn2006.html#RahmaniherisS06 Farhad Mehdipour Morteza Saheb Zamani Hamid Reza Ahmadifar Mehdi Sedighi Kazuaki J. Murakami Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. 2006 conf/ipps/2006 IPDPS https://doi.org/10.1109/IPDPS.2006.1639611 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2006.1639611 db/conf/ipps/ipdps2006.html#MehdipourZASM06 Hamid Safizadeh Hamid Noori Mehdi Sedighi Ali Jahanian 0001 Neda Zolfaghari Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms. 227-230 2005 conf/dsd/2005 DSD https://doi.org/10.1109/DSD.2005.37 https://doi.ieeecomputersociety.org/10.1109/DSD.2005.37 db/conf/dsd/dsd2005.html#SafizadehNSJZ05 Farhad Mehdipour Morteza Saheb Zamani Mehdi Sedighi Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. 372-378 2005 conf/dsd/2005 DSD https://doi.org/10.1109/DSD.2005.67 https://doi.ieeecomputersociety.org/10.1109/DSD.2005.67 db/conf/dsd/dsd2005.html#MehdipourZS05 Mehrdad Najibi Kamran Saleh Mohsen Naderi Hossein Pedram Mehdi Sedighi Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). 269 2005 conf/fpga/2005 FPGA https://doi.org/10.1145/1046192.1046243 db/conf/fpga/fpga2005.html#NajibiSNPS05 Kamran Saleh Mehrdad Najibi Mohsen Naderi Hossein Pedram Mehdi Sedighi A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. 296-301 2005 conf/glvlsi/2005 ACM Great Lakes Symposium on VLSI https://doi.org/10.1145/1057661.1057733 db/conf/glvlsi/glvlsi2005.html#SalehNNPS05 Mehrdad Najibi Kamran Saleh Mohsen Naderi Hossein Pedram Mehdi Sedighi Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. 63-69 2005 conf/rsp/2005 IEEE International Workshop on Rapid System Prototyping https://doi.org/10.1109/RSP.2005.41 https://doi.ieeecomputersociety.org/10.1109/RSP.2005.41 db/conf/rsp/rsp2005.html#NajibiSNPS05 Hamid Reza Ahmadifar Mahdi Aminian Mona Arabzadeh Ehsan K. Ardestani Mohammad Reza Bagheri Samaneh Emami Maryam Eslamy Mehran S. Fallah Sam Farrokhi Sohrab Mortazavi Ghalati Reza Gholami Foroogh Haddadi Mehdi Harounabadi Hamid Hassanpour Mahboobeh Houshmand Monireh Houshmand Koji Inoue Ali Jahanian 0001 Ali Reza Manashty Sayed-Amir Marashi Kourosh Marjoei Farhad Mehdipour Naser MohammadZadeh Mohammad Hadi Mottaghi Kazuaki J. Murakami Mohsen Naderi Mehrdad Najibi Eesa Nikahd Hamid Noori Hossein Pedram M. Rahmaniheris Mehdi Saeedi Mahya Saffarpour Hamid Safizadeh Kamran Saleh Mohammad Hossein Samavatian Zahra Sasanian Amir Bavafa Toosi Maryam Yazdani Morteza Saheb Zamani Behrouz Zolfaghari Neda Zolfaghari